3D Chip Stacking with Peripheral Pad Expansion for TSV-Free Integration
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Solution Overview
Problem
Current three-dimensional integration technologies for multiple functional chips face limitations, including limited chip types, complex manufacturing processes, and low yield rates due to the need for through-silicon via technology, which restricts compatibility and performance.
Innovation Solution
A three-dimensional integrated system with a compatible chip architecture that allows for the alignment and bonding of functional chips with expanded peripheral pads, enabling independent manufacturing and electrical connection of different chip types, simplifying the integration process and increasing yield rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If through-silicon via (TSV) technology is used to realize three-dimensional integration, then different structures and types of chips can be integrated, but the manufacturing process becomes complicated and the yield rate decreases
Solution Approach 1:
The chip is divided into a functional chip area and a peripheral area, with pads segregated into functional pads and peripheral pads. This segmentation allows different chip types to be integrated while simplifying the bonding process by separating critical functional connections from inter-chip connections.
Solution Approach 2:
The peripheral pads are extracted and arranged in a dedicated peripheral area around the functional chip. This extraction removes the complexity of integrating both functional and inter-chip pads in the same area, enabling simpler manufacturing processes while maintaining compatibility with different chip types.
2Adaptability or versatility
If through-silicon via (TSV) technology is used to realize three-dimensional integration, then different structures and types of chips can be integrated, but the manufacturing process requires multiple etching and deposition steps
Solution Approach 1:
The pad structure is segmented into functional pads within the functional chip and peripheral pads in the peripheral area. This segmentation eliminates the need for complex through-silicon via etching and deposition steps, as peripheral pads can be directly bonded without requiring TSV processing.
Solution Approach 2:
The peripheral pads are extracted to a separate peripheral area, removing them from the functional chip structure. This extraction allows peripheral pads to be processed and bonded independently without requiring the complex multi-step TSV manufacturing process.
3Ease of manufacture
If monolithic three-dimensional integration based on CMOS technology is used, then manufacturing is simplified, but the types of integrated functional chips are limited and performance is not optimal
Solution Approach 1:
The chip is segmented into a functional chip area that can be manufactured using various technologies (not limited to CMOS) and a peripheral area for pad arrangement. This segmentation allows different functional chips with optimal performance to be integrated while maintaining a unified bonding interface.
Solution Approach 2:
The peripheral pad structure serves multiple functions: it provides electrical connections for the functional chip, enables bonding with other chips, and accommodates different chip types. This universal interface design allows the system to integrate diverse functional chips while maintaining manufacturing simplicity.
Data Source
AI summary
The disclosure a three-dimensional integrated system with a compatible chip and a manufacturing method thereof, which extends at least one functional chip to form an expanded chip including a functional chip and a peripheral pad. And a pad of the functional chip is electrically drawn out to the peripheral pads by rewiring. Based on an alignment bonding of the two expanded chips corresponding to the peripheral pads, or based on an alignment bonding of the functional chip and the expanded chip, an electrical connection and three-dimensional integration between two functional chips is completed simply and effectively. An integrated connection between two independent functional chips is realized based on the peripheral expanded pads. Each functional chip may be manufactured with its own independent process system.