3D Chip Stacking Power/Thermal Via for Routing and Heat Dissipation
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Solution Overview
Problem
State-of-the-art mobile application devices face power routing issues and high power density challenges in three-dimensional (3D) stacked chip architectures, which are exacerbated by the increasing number of interconnect levels and power distribution losses, posing a bottleneck for design advancements.
Innovation Solution
A power and/or thermal via is integrated into a 3D stacked chip design, extending from the backside of a second die to the back-end-of-line (BEOL) layer, enabling independent power supply and thermal management for both dies, with features like hybrid copper bonding and redistribution layers to enhance power density and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple dies are stacked in 3D architecture to reduce form factor, then device integration density is improved, but power routing issues and power distribution losses worsen
Solution Approach 1:
The power distribution system is segmented into multiple independent power vias that extend from the backside of the second die to the BEOL layer. This segmentation allows power to be distributed through multiple separate pathways rather than relying on a single power routing path, thereby reducing power distribution losses while maintaining the compact 3D stacked architecture.
Solution Approach 2:
The patent utilizes the vertical dimension by extending power vias from the backside of the second die through the substrate to the BEOL layer. This three-dimensional power routing approach eliminates the need for additional horizontal interconnect layers, maintaining the compact form factor while improving power distribution efficiency through the vertical Z-dimension.
2Adaptability or versatility
If the number of interconnect levels is increased to support more devices, then electrical connection capability is improved, but device complexity and manufacturing intricacy worsen
Solution Approach 1:
The via structure serves multiple functions simultaneously: it acts as a power via for electrical connection, a thermal via for heat dissipation, and a mechanical support structure. This multi-functionality eliminates the need for separate dedicated power and thermal management structures, thereby reducing manufacturing complexity while maintaining enhanced electrical connection capabilities.
Solution Approach 2:
The patent merges the power distribution function and thermal management function into a single integrated via structure. By combining these functions, the design reduces the total number of separate interconnect levels and manufacturing steps required, thereby reducing device complexity and manufacturing intricacy while maintaining robust electrical connection capability.
3Power
If power density is increased to support high-performance applications, then electrical performance is improved, but thermal management challenges worsen
Solution Approach 1:
The via structure acts as an intermediary that simultaneously handles both power delivery and thermal dissipation. The conductive material within the via serves as a mediator that can transport electrical power from the BEOL layer to the dies while also conducting heat away from the high-power-density regions through its thermal conductivity, thereby addressing both power and thermal management requirements.
Solution Approach 2:
The via structure utilizes composite material properties, combining high electrical conductivity for power delivery with high thermal conductivity for heat dissipation. This composite functionality allows the same structural element to support high power density applications while effectively managing the resulting thermal challenges through its dual conductive properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively addresses power routing issues and improves thermal management, supporting high electrical performance and small form factor requirements in 3D chip stacking, aligning with Moore's law advancements.
Implementation Method 1
a via extending from the backside surface of the second die to a back-end-of-line (BEOL) layer of the second die
Implementation Method 2
power and/or thermal via is integrated into a 3D stacked chip design... enabling independent power supply and thermal management
Data Source
AI summary
A three-dimensional (3D) stacked chip is described. The 3D stacked chip includes a first die having a front-side surface and a backside surface, opposite the front-side surface. The backside surface on a front-side surface of a first redistribution layer (RDL). The 3D stacked chip also includes a second die having a front-side surface on the front-side surface of the first die and a backside surface being distal from the first RDL. The 3D stacked chip further includes a via extending from the backside surface of the second die to a back-end-of-line (BEOL) layer of the second die.