3D Chip Selection via Scan ID Matching in Multi-Chip Packages
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Solution Overview
Problem
Current 3D packaging technologies for integrated circuit chips face challenges in accessing individual die within a stack without complex and costly processes, such as unique identifier marking and decoder configuration, which complicate the packaging and increase costs.
Innovation Solution
Each die in a multi-chip package is equipped with nonvolatile memory to store unique IDs, allowing control logic to compare input IDs with stored IDs and assign access IDs, enabling selective access to individual die during operation without pre-identification during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If unique identifier marking and decoder configuration are implemented during wafer manufacture, then individual die can be identified and accessed, but manufacturing complexity and costs increase
Solution Approach 1:
Unique identifiers (scan IDs) are assigned to each die during wafer manufacture in advance, before packaging. This preliminary action eliminates the need for complex decoder configuration during packaging, as the identifiers are already embedded in the die themselves.
Solution Approach 2:
Each die carries its own unique scan ID that enables self-identification during package testing. The die does not require external decoder configuration or complex handling to be identified, as the identifier is inherently part of the die structure.
2Reliability
If special handling and tracking of individual die are implemented, then correct die selection is achieved, but manufacturing costs and process complexity increase
Solution Approach 1:
The die themselves provide identification information through embedded scan IDs, eliminating the need for external tracking systems or special handling procedures. Each die is self-identifying, which simplifies manufacturing and reduces costs.
Solution Approach 2:
Instead of physically marking or tagging each die with unique identifiers, the patent uses digital copy of identifier data stored in nonvolatile memory on each die. This virtual identification system is cheaper and simpler than physical marking methods.
3Reliability
If unique lithographic patterns are used for each die, then decoder configuration is enabled, but lithographic mask costs and manufacturing complexity increase
Solution Approach 1:
The identification function is extracted from the lithographic process and embedded directly in the die as scan IDs. This separates the identification mechanism from the decoder configuration, allowing standard lithographic processes to be used without complex unique patterns for each die.
Solution Approach 2:
A single standardized lithographic process can be used for all die in the wafer, as each die receives the same basic pattern. The unique identification is achieved through the scan ID assignment rather than through unique lithographic patterns, making the process universal and simpler.
4Reliability
If micro-balls and external control connections are used for chip identification, then individual chip selection is enabled, but chip area and connection resources are consumed
Solution Approach 1:
The identification function is extracted from external physical features (micro-balls, control connections) and embedded within the chip itself as scan IDs in nonvolatile memory. This eliminates the need for additional external identification structures that consume chip area.
Solution Approach 2:
The identification data is merged with the chip's internal memory structure rather than requiring separate external identification components. The scan ID is stored in nonvolatile memory cells that are part of the chip's existing architecture, eliminating the need for additional micro-balls or control connections.
Data Source
AI summary
A multi-chip package with die having shared input and unique access IDs. A unique first ID is assigned and stored on die in a die lot. A set of die is mounted in a multi-chip package. Free access IDs are assigned by applying a sequence of scan IDs on the shared input. On each die, the scan ID on the shared input is compared with the unique first ID stored on the die. Upon detecting a match, circuitry on the die is enabled for a period of time to write an access ID in nonvolatile memory, whereby one of the die in the multi-chip package is enabled at a time. Also, the shared input is used to write a free access ID in nonvolatile memory on the one enabled die in the set. The unique first IDs can be stored during a wafer level sort process.