3D Chip Shared Clock Network for Low-Skew Signal Distribution
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Solution Overview
Problem
The challenge is to increase the number of transistors in an IC chip beyond the limits imposed by the end of Moore's law, as the maximum number of transistors that can be defined on a semiconductor substrate is being reached.
Innovation Solution
A three-dimensional (3D) circuit is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and share one or more interconnect layers that distribute power, clock, and/or data-bus signals. The shared interconnect layers include interconnect segments that carry these signals, and the dies are bonded using direct bonding techniques such as DBI technology to establish direct metal-to-metal connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more interconnect layers are added to distribute signals to more dies, then signal distribution capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Multiple IC dies share common interconnect layers (power, clock, data-bus) instead of each die having dedicated interconnect layers. The shared interconnect layers are formed above the stacked dies, allowing signal distribution to multiple dies simultaneously, reducing overall complexity while maintaining adaptability.
Solution Approach 2:
The shared interconnect layers serve multiple functions: distributing power, clock, and data-bus signals to multiple different IC dies simultaneously. This multi-functional approach replaces what would traditionally require separate dedicated interconnect structures for each die and signal type.
2Productivity
If IC dies are stacked vertically to increase transistor density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
IC dies are stacked vertically in a nested arrangement where multiple dies occupy the same footprint area in three-dimensional space. This nesting approach increases effective transistor density without requiring larger chip areas, while the shared interconnect layers provide a unified interface that simplifies alignment requirements compared to traditional wire-bonding methods.
3Reliability
If each IC die has dedicated interconnect layers for power, clock, and data signals, then reliability is improved, but device complexity increases
Solution Approach 1:
Dedicated interconnect layers for power, clock, and data-bus signals are merged into shared interconnect layers that serve multiple IC dies simultaneously. This consolidation reduces the total number of interconnect layers while maintaining reliable signal distribution through the shared infrastructure.
Solution Approach 2:
The shared interconnect layers are designed with universal functionality to distribute multiple signal types (power, clock, data-bus) to multiple different IC dies through the same physical infrastructure, reducing complexity while ensuring reliable delivery of all signal types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a higher density of interconnects between IC dies, reducing the capacitive load and signal skew, and enabling more efficient distribution of power, clock, and data signals. By sharing interconnect layers, the overall number of interconnect layers required is reduced, optimizing space and performance.
Implementation Method 1
The shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
Data Source
AI summary
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.