3D Chip Shared Data Bus With Stacked Interconnect Layers
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Solution Overview
Problem
The end of Moore's law has been reached, limiting the number of transistors that can be defined on a semiconductor substrate, necessitating new advances to increase transistor density in IC chips.
Innovation Solution
A 3D circuit is formed by stacking two or more IC dies to share interconnect layers for power, clock, and data-bus signals, utilizing direct bonding techniques like Cu-Cu metallic bonding and DBI technology to establish direct connections between the top interconnect layers, allowing orthogonal wiring directions to optimize signal routing and reduce capacitive load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more interconnect layers are added to accommodate more transistors, then transistor density increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from two-dimensional planar stacking to three-dimensional interlocking architecture. Dies are stacked with alternating orientations (first die in first orientation, second die in second orientation different from first), creating a 3D interlocking structure that shares interconnect layers vertically while maintaining horizontal routing. This dimensional change allows multiple dies to share common interconnect layers, reducing the total number of interconnect layers needed compared to traditional 2D stacking.
2Adaptability or versatility
If more interconnect layers are added to support additional circuits, then functional capability increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges interconnect layers from multiple dies into shared common interconnect layers. Instead of each die having separate dedicated interconnect layers, the 3D interlocking architecture allows adjacent dies to share interconnect layers vertically. This merging reduces the total number of interconnect layers that require precise manufacturing and alignment, while still supporting the functional capabilities of all dies in the stack.
3Area of stationary object
If traditional 2D stacking is used to increase transistor density, then space efficiency improves, but signal path length and capacitive load increase
Solution Approach 1:
The patent introduces vertical sharing of interconnect layers through 3D interlocking, allowing signals to be distributed both horizontally within a die and vertically to adjacent dies. This creates shorter signal paths compared to 2D stacking where all routing must occur within the plane of a single die. The vertical dimension provides direct access to shared resources in adjacent dies, reducing the need for long lateral signal paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases transistor density by reducing the number of interconnect layers, shortening signal paths, and optimizing space usage, resulting in improved performance and cost efficiency by sharing power, clock, and data-bus circuits across dies.
Implementation Method 1
The shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the shared interconnect layers are bonded together through a direct bonding process that establishes direct-contact metal-to-metal bonding, oxide bonding, or fusion bonding between these two sets of interconnect layers. An example of such bonding is copper-to-copper (Cu-Cu) metallic bonding between two copper conductors in direct contact.
Implementation Method 2
the shared interconnect layers are bonded together through a direct bonding process that establishes direct-contact metal-to-metal bonding, oxide bonding, or fusion bonding between these two sets of interconnect layers
Data Source
AI summary
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.