3D Chip Sharing Data Bus via Direct Bonding
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Solution Overview
Problem
The limitations of Moore's Law, as semiconductor technology approaches the maximum number of transistors that can be defined on a semiconductor substrate, necessitate innovative approaches to increase transistor density in IC chips.
Innovation Solution
A three-dimensional (3D) circuit is formed by stacking two or more integrated circuit (IC) dies to share interconnect layers for power, clock, and data-bus signals, utilizing direct bonding techniques like DBI to establish a large number of short, high-density connections between the top interconnect layers, allowing orthogonal wiring directions to optimize signal routing and reduce capacitive load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more interconnect layers are added to a single IC die to increase transistor density, then the number of transistors that can be defined increases, but the manufacturing complexity and signal path length increase
Solution Approach 1:
The patent transitions from two-dimensional planar stacking of interconnect layers on a single die to three-dimensional vertical stacking of multiple IC dies. By moving to the third dimension (vertical stacking), the system achieves higher transistor density without proportionally increasing the complexity of interconnect layers on each individual die, as the interconnect functionality is distributed across multiple stacked dies rather than concentrated in numerous layers on one die.
2Adaptability or versatility
If more interconnect layers are added to distribute power, clock and data-bus signals, then signal distribution capability improves, but capacitive load and signal path length increase
Solution Approach 1:
The patent segments the interconnect functionality by distributing it across multiple stacked IC dies rather than concentrating all interconnect layers on a single die. This segmentation reduces the capacitive load on any individual interconnect layer while maintaining comprehensive signal distribution capability, as each die in the stack handles a portion of the interconnect function.
Solution Approach 2:
By transitioning to three-dimensional vertical stacking, the patent reduces the horizontal spread and capacitive coupling within each interconnect layer. The vertical arrangement allows for shorter signal paths and reduced capacitive load compared to adding numerous horizontal layers on a single die, while still achieving comprehensive signal distribution across the entire system.
3Quantity of substance
If direct bonding techniques are used to stack IC dies, then connection density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring the interconnect layers on each IC die before stacking, ensuring that the bonding interfaces are properly aligned and prepared in advance. This preliminary preparation reduces the manufacturing precision requirements during the actual bonding process, as the components are already positioned optimally for high-density connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor density by reducing the number of interconnect layers needed, shortening signal paths, and minimizing capacitive load, thereby improving the cost and performance of chip stacks by sharing power, clock, and data-bus circuits across multiple dies.
Implementation Method 1
the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other... the top interconnect layers bonded to each other through a direct bonding process that establishes direct-contact metal-to-metal bonding
Data Source
AI summary
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.