3D Chip Package Shielded Cavities for Crosstalk Reduction

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Solution Overview

Problem

In 3D IC packages, close proximity of components leads to electrical and magnetic crosstalk, noise interference, and heat transmission issues, which existing technologies fail to adequately address, especially in System on Chip applications where sensitive analog dies are co-packaged with noisy digital circuits.

Innovation Solution

A 3D chip package design featuring a carrier substrate with shielded cavities and multiple shield layers for electrical, magnetic, optical, and thermal isolation between IC structures, utilizing metal layers to act as Faraday cages and heat sinks, reducing parasitic interactions and enhancing signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple IC structures are co-packaged in close proximity in a 3D IC package, then device integration density and productivity are improved, but electrical and magnetic crosstalk and noise interference increase

Engineering Contradiction:
Improvedevice integration densityVSAvoidelectrical and magnetic crosstalk
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

A shield layer comprising a conductive material is disposed between the first and second IC structures to act as an intermediary that blocks electrical and magnetic fields. The shield layer is connected to a ground voltage, providing a reference potential that prevents crosstalk between adjacent IC structures while allowing them to remain in close proximity for high integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The package structure is segmented into isolated regions by dividing the space between IC structures with shield layers. This segmentation creates electrically and magnetically isolated zones, allowing multiple IC structures to be packaged closely without interference between them.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple IC structures are co-packaged in close proximity in a 3D IC package, then device integration density is improved, but noise interference increases

Engineering Contradiction:
Improvedevice integration densityVSAvoidnoise interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The shield layer serves as a mediator that blocks electromagnetic noise from propagating between IC structures. By being connected to ground voltage, it absorbs and dissipates noise energy, preventing it from interfering with sensitive circuits in adjacent IC structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple IC structures are co-packaged in close proximity in a 3D IC package, then device integration density is improved, but heat transmission issues worsen

Engineering Contradiction:
Improvedevice integration densityVSAvoidheat transmission
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The shield layer acts as a thermal intermediary between IC structures. It can be designed with specific thermal conductivity properties to either conduct heat away from hot spots or provide thermal isolation, depending on the thermal management requirements of the co-packaged IC structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces electrical and magnetic crosstalk, noise interference, and heat transmission, enabling the co-packaging of heterogeneous IC structures with improved signal-to-noise ratio and reduced complexity, while allowing for smaller, more efficient chip designs with increased yield and cost-effectiveness.

Implementation Method 1

A shield layer may be disposed between the carrier substrate and the first IC structure and/or the second IC structure for isolating the first IC structure and/or the second IC structure

Methodology Applied
Scientific EffectElectrostatic shielding: Faraday Cage

Implementation Method 2

utilizing metal layers to act as Faraday cages and heat sinks

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 3

utilizing metal layers to act as Faraday cages and heat sinks

Methodology Applied
Scientific EffectHeat sinking: Heat Sink

Data Source

PatentUS8686543B23D chip package with shielded structures
Publication Date: 2014.04.01 MAXIM INTEGRATED PROD INC
  • US8686543B2 patent drawing
  • US8686543B2 patent drawing
  • US8686543B2 patent drawing

AI summary

A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.