3D Redistribution Substrate Stack for Compact Chip Cooling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages face challenges in achieving a small form factor, high performance, and effective heat dissipation while maintaining reliability due to increased power consumption and complexity in chip connections.
Innovation Solution
A semiconductor package design featuring multiple redistribution substrates and through-posts, with aligned chip configurations and a heat dissipation block, along with sealants to enhance heat transfer and reduce connection paths, ensuring efficient heat dissipation and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple chips are connected in a conventional layout, then connection complexity increases, but form factor size increases and heat dissipation becomes difficult
Solution Approach 1:
The patent transitions from a conventional planar layout to a three-dimensional stacked configuration where chips are arranged vertically along the Z-axis. Redistribution substrates are positioned at different heights (first redistribution substrate at lower level, second redistribution substrate at upper level), enabling spatial separation of connection paths and reducing lateral interference. This vertical stacking approach compresses the device footprint while maintaining complex inter-chip connectivity.
Solution Approach 2:
The patent implements a nested hierarchical structure where chips are stacked upon redistribution substrates which themselves are stacked upon other chips. Specifically, the first chip is connected to the first redistribution substrate, which connects to the second chip, which connects to the second redistribution substrate, creating a nested chain of connections. This nesting allows multiple connection layers to be compacted into a vertical stack, reducing the overall form factor while preserving connection complexity.
2Power
If power consumption increases to achieve higher performance, then performance improves, but heat dissipation becomes more difficult
Solution Approach 1:
The patent extracts the heat dissipation function as a separate, dedicated component positioned at the bottom of the stack. The heat dissipation block is disposed beneath the first chip and first redistribution substrate, physically separating the heat management system from the active computing components. This extraction allows heat to be removed from the high-performance chips without interfering with their operation, enabling sustained high power consumption and performance.
Solution Approach 2:
The first redistribution substrate serves as a thermal intermediary between the heat-generating first chip and the heat dissipation block below. The substrate conducts heat away from the chip while distributing it to the dedicated heat dissipation structure. This intermediary approach enables efficient heat transfer from high-power components without requiring direct contact between chips and heat sinks, maintaining performance while managing thermal loads.
3Volume of moving object
If chip size is reduced to achieve smaller form factor, then form factor decreases, but reliability of connections deteriorates
Solution Approach 1:
The patent compensates for reduced chip dimensions by extending connection paths into the vertical dimension. Through-posts extend through the thickness of redistribution substrates, creating three-dimensional connection pathways. This vertical extension of connection paths allows small chips to maintain reliable electrical connections without requiring larger lateral dimensions, as connectivity is achieved through the Z-axis rather than relying solely on planar contact areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a compact form factor, enhanced heat dissipation, and improved reliability by optimizing chip connections and heat management, while maintaining signal integrity and reducing manufacturing complexity.
Implementation Method 1
a heat dissipation block on the second side of the third redistribution substrate
Implementation Method 2
a sealant located between the first redistribution substrate and the second redistribution substrate and covering side surfaces of the first through-post and the second through-post, a side surface and an upper surface of the first semiconductor chip, and a side surface and a lower surface of the second semiconductor chip
Data Source
AI summary
The semiconductor package includes a first redistribution substrate, a first semiconductor chip on a first side the first redistribution substrate, a first through-post on a second side of the first redistribution substrate, a second redistribution substrate on the first semiconductor chip and the first through-post, a second semiconductor chip on a second side of the second redistribution substrate, a second through-post on a first side of the second redistribution substrate, a third redistribution substrate on the second semiconductor chip and the second through-post, a heat dissipation block on a second side of the third redistribution substrate, and a semiconductor device on a first side of the third redistribution substrate. The first side of the first redistribution substrate, the second redistribution substrate, and the third redistribution substrate, are each spaced apart from a respective second side in a horizontal direction and the first sides are each aligned in a vertical direction.