3D Chip Stack Power Scheduling via TSV Subset Segmentation
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Solution Overview
Problem
As the number of layers in a 3D chip stack increases, existing technologies face challenges in delivering sufficient power due to voltage droop caused by Through-Silicon-Vias (TSVs) being unable to handle the power requirements for a large number of memory requests, with current designs limited to fewer than 10 layers.
Innovation Solution
A computer-implemented method and system that schedules memory requests in a 3D chip stack by determining power delivery limits for subsets of TSVs and using a scorecard-based scheduler to manage power delivery across memory layers, optimizing read/write requests to prevent exceeding power budgets and mitigate voltage droop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in a 3D chip stack is increased, then the memory capacity and performance are improved, but the power delivery capability deteriorates due to voltage droop in TSVs
Solution Approach 1:
The patent applies preliminary action by determining power delivery limits for each TSV subset before scheduling memory requests. The controller pre-calculates the power capacity of each TSV subset and uses this information to make informed scheduling decisions, preventing power overload before it occurs. This allows the system to support more memory layers by proactively managing power distribution across the stack.
2Productivity
If more memory requests are handled simultaneously, then the productivity is improved, but the voltage droop increases causing power delivery failure
Solution Approach 1:
The patent applies segmentation by dividing the TSVs into multiple subsets, where each subset serves a specific group of memory banks. This segmentation allows the controller to distribute memory requests across different TSV subsets, preventing any single subset from being overloaded. By segmenting the power delivery paths, the system can handle more simultaneous memory requests while maintaining stable voltage levels and avoiding droop.
3Reliability
If the power budget per TSV subset is limited, then the reliability is improved by preventing voltage droop, but the memory operation efficiency decreases
Solution Approach 1:
The patent applies dynamics by implementing a dynamic scheduling mechanism that adapts to the power delivery limits of each TSV subset. The controller dynamically assigns memory requests to appropriate TSV subsets based on their power capacity and current load, optimizing the balance between reliability and efficiency. This dynamic approach allows the system to maintain stable power delivery while maximizing memory operation throughput through intelligent request distribution.
Data Source
AI summary
A computer implemented method and system for managing power in a 3D chip stack formed of multiple memory layers each having a plurality memory banks and a plurality of Through-Silicon-Vias (TSVs) connecting the memory banks. The TSVs are arranged in a plurality of subsets, each subset of TSVs connecting a corresponding vertical stack of memory banks aligned across a plurality of memory layers. The method includes determining a power delivery budget for each subset of TSVs connecting the corresponding vertical stack of memory banks based on memory requests, keeping track of memory requests to the memory banks of each vertical stack of memory banks and scheduling the memory requests to the memory banks of each vertical stack of memory banks based on the power budget. The memory controller is configured with a scorecard scheduler to manage the memory requests based on the power budget.