3D Stacked Chip Tile Pairing for Low-Latency Data Flow
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Solution Overview
Problem
Existing 3D stacked semiconductor devices face challenges in efficiently routing data channels due to inadequate Placer and Router solutions, leading to routing congestion and low bandwidth, which limits data transfer capabilities.
Innovation Solution
A method for forming a 3D stacked device by aligning semiconductor chips vertically, optimizing tile-to-tile and pin-to-pin connections to minimize latency and maximize bandwidth, using network-on-chip components, programmable logic, and artificial intelligence engine components, and employing conductive traces and through silicon vias for inter-chip data movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D stacked device uses vertical connectivity among components in different layers, then the number of connections increases compared to 2D devices, but routing congestion and low bandwidth issues arise in inter-chip communication
Solution Approach 1:
The patent segments the inter-chip communication into multiple hierarchical levels: intra-tile connections, inter-tile connections within a chip, and inter-chip connections through TSVs. This segmentation allows routing to be managed in discrete, manageable units rather than as a monolithic complex network, reducing overall routing congestion while maintaining high connection density
Solution Approach 2:
The patent transitions from 2D substrate routing to 3D vertical routing by stacking multiple semiconductor chips and using through-silicon vias (TSVs) for inter-layer connectivity. This dimensional change enables significantly more connections by utilizing the vertical Z-axis, transforming the routing problem from a planar constraint to a volumetric solution that achieves higher bandwidth without proportionally increasing routing complexity
2Productivity
If 3D stacked device achieves high bandwidth memory communication, then data transfer capacity increases, but tile-to-tile pairing and routing optimization becomes increasingly complex
Solution Approach 1:
The patent performs preliminary tile-to-tile pairing and routing optimization during the design and fabrication stages using automated placement and routing tools. By pre-establishing optimal connection paths and pairings before the device is operational, the complex optimization problem is solved in advance, allowing the device to achieve high data transfer capacity without requiring complex real-time routing decisions during operation
Solution Approach 2:
The patent optimizes specific parameters such as TSV placement locations, tile pairing configurations, and bus routing paths to minimize signal delay and maximize bandwidth. By systematically adjusting these physical and electrical parameters during design, the device achieves high productivity in data transfer while managing routing complexity through parameter optimization rather than structural complexity
Data Source
AI summary
A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.