3D Chip Voltage Droop Mitigation via Layer Segmentation
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Solution Overview
Problem
3D stacked chip systems face significant voltage droop issues due to parasitic impedance and current fluctuations, leading to power integrity problems and reliability degradation, with existing solutions being costly and inefficient, especially as transistor size decreases and layer count increases.
Innovation Solution
A multichip system with vertically stacked dies equipped with voltage violation sensing units and frequency tuning units, allowing for independent voltage and frequency control of each core, and a thread scheduling method that estimates and mitigates intrinsic droop intensity by strategically allocating threads across layers to minimize voltage interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 3D stacked chip systems are used to increase device density and reduce wire length, then performance and power efficiency are improved, but voltage droop and power integrity issues worsen due to parasitic impedance and current fluctuations
Solution Approach 1:
The patent segments the power delivery network into multiple independent control regions corresponding to different die layers. Each layer has its own voltage regulator and control circuitry, allowing independent voltage and frequency management for each stacked die. This segmentation enables localized power integrity optimization without affecting other layers, directly addressing the voltage droop issue while maintaining the high-density 3D architecture.
Solution Approach 2:
The patent implements dynamic voltage and frequency scaling (DVFS) for each die layer based on real-time power consumption monitoring. The system continuously adjusts voltage and frequency parameters to match actual computational workload, preventing excessive current fluctuations that cause voltage droop. This dynamic adaptation maintains power integrity while enabling the system to achieve high performance when needed.
2Quantity of substance
If transistor size is reduced and layer count is increased to improve density, then device capacity increases, but voltage droop becomes more severe due to higher parasitic impedance
Solution Approach 1:
The patent applies local quality optimization by tailoring voltage regulator parameters, decoupling capacitance values, and power mesh configurations to each specific die layer's characteristics. Each layer's power delivery network is optimized according to its unique parasitic impedance profile, transistor density, and computational workload patterns. This localized optimization effectively mitigates voltage droop in high-density regions without compromising overall system performance.
3Device complexity
If conventional power delivery networks are used in 3D chips, then implementation is simple, but voltage violations occur due to insufficient mitigation of intrinsic droop intensity
Solution Approach 1:
The patent implements a feedback control mechanism where voltage sensors monitor real-time voltage levels in each die layer and feed this information back to voltage regulators. When voltage droop is detected, the system automatically adjusts regulator output and triggers frequency scaling to reduce current demand. This closed-loop feedback system maintains voltage stability without requiring overly complex power delivery infrastructure.
Data Source
AI summary
The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.