3D Chiplet Memory-Logic Stacking for Dense CIM Interconnects
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Solution Overview
Problem
Current compute-in-memory (CIM) and compute-near-memory (CNM) architectures face challenges in integrating with existing processors due to device node mismatches in two-dimensional (2D) SoC designs and interconnect density requirements in three-dimensional (3D) stacked chips, limiting their feasibility for energy-efficient computing in edge accelerators.
Innovation Solution
The proposed solution involves a 3D chiplet architecture with wafer-on-wafer stacked memory and control tiers, utilizing direct bonds and oxide bonds to simplify interconnects, and through-silicon vias (TSVs) for data links between logic and memory tiers, enabling high-density, low-power CIM chiplets compatible with CMOS technology for integration with CPUs, GPUs, and AI accelerators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 2D SoC design is used for CIM architecture, then device node mismatch challenges occur between NVM function block and control logic block, but integration with existing processors is simplified
Solution Approach 1:
The patent transitions from 2D SoC design to 3D stacked chiplet architecture, stacking memory die and logic die vertically to achieve both integration compatibility and device node matching. The 3D configuration allows independent optimization of memory and logic layers while maintaining interconnect density through vertical stacking with microbumps and TSVs.
2Adaptability or versatility
If 3D stacked chips with microbump technology are used, then interconnect density requirements for CIM architecture partitioning and re-integrating are not fulfilled, but stacking of memory and logic tiers is achieved
Solution Approach 1:
The patent segments the CIM architecture into separate memory die and logic die that are stacked vertically. This segmentation allows independent optimization of each layer while achieving high interconnect density through the stacking interface using microbumps and through-silicon vias, enabling efficient partitioning and re-integration of CIM components.
3Adaptability or versatility
If monolithic 3DIC is used for memory architecture, then feasibility for CIM and CNM implementations is limited, but three-dimensional integration is achieved
Solution Approach 1:
The patent divides the monolithic 3DIC into separate stackable chiplets including memory die and logic die. This segmentation reduces the complexity of monolithic integration while maintaining three-dimensional integration benefits, allowing flexible CIM and CNM implementations through heterogeneous stacking of specialized functional blocks.
Data Source
AI summary
A semiconductor structure, includes a logic die, a memory die stack bonded to the logic die by a first oxide bond, and including a first pair of memory dies bonded together by a first direct bond, and a first through silicon via (TSV) in the logic die and extending across the first oxide bond and electrically connecting the logic die to the first pair of memory dies.