3D Chiplet Architecture for High-Density Compute and Memory
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Solution Overview
Problem
Conventional two-dimensional approaches for increasing processing power in integrated circuits are limited by size constraints, leading to inefficiencies in communication and processing capabilities.
Innovation Solution
A three-dimensional architecture for integrated circuits, where computing chiplets are stacked atop random access memory chiplets, allowing for low-latency communication and increased processing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional processing elements are added along the width and length dimensions of the die in a two-dimensional approach, then processing power is increased, but the die area increases and is limited by size constraints
Solution Approach 1:
The patent transitions from a two-dimensional die layout to a three-dimensional stacked architecture where multiple chiplets are vertically stacked and interconnected. This dimensional change allows processing elements to be added in the vertical dimension rather than expanding the horizontal die area, thereby increasing processing power without proportionally increasing the footprint area.
2Productivity
If more processing elements are added to increase processing power, then compute capacity increases, but communication latency increases due to larger distances between elements
Solution Approach 1:
By stacking chiplets vertically and implementing direct vertical interconnections, the patent reduces the communication distance between processing elements compared to horizontal expansion. The three-dimensional interconnect architecture provides shorter signal paths through the stack, thereby reducing communication latency while maintaining high compute capacity.
3Productivity
If die size is increased to accommodate more processing elements, then processing power increases, but manufacturing precision and yield deteriorate due to larger die size
Solution Approach 1:
The patent divides the computing system into multiple smaller, independent chiplets that are manufactured separately and then stacked together. This segmentation allows each chiplet to be manufactured with high precision using standard fabrication processes, avoiding the yield penalties associated with manufacturing large monolithic dies. The modular chiplet approach enables high processing power through parallel assembly of multiple precision-manufactured units.
4Quantity of substance
If memory capacity is increased using conventional two-dimensional approaches, then memory capacity increases, but the area footprint increases significantly
Solution Approach 1:
The patent implements memory chiplets stacked vertically in a three-dimensional configuration, allowing memory capacity to be increased by utilizing the vertical dimension. This stacking approach provides high memory density without proportionally increasing the horizontal area footprint, achieving superior memory capacity per unit area compared to conventional two-dimensional memory arrays.
Data Source
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AI summary
Three-dimensional chip architecture is described herein. In one example aspect, an integrated circuit may include an interposer layer. The integrated circuit may further include a plurality of random access memory chiplets stacked atop the interposer layer, and a plurality of compute chiplets. The plurality of compute chiplets may be stacked atop a respective random access memory chip of the plurality of random access memory chiplets, such that the plurality of compute chiplets may be in electrical communication with the respective random access memory chip of the plurality of random access memory chiplets.