3D Processing-SRAM Chiplet Stacking for High-Bandwidth Integration
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Solution Overview
Problem
Existing electronic devices face challenges in integrating processing and static random-access memory (SRAM) capabilities due to differing scaling rates, leading to insufficient performance, increased size, and cost, with alternatives like DRAM integration or multi-chip modules failing to meet performance requirements.
Innovation Solution
A three-dimensional integration of processing chiplets and SRAM chiplets is achieved by stacking multiple SRAM chiplets on both sides of a logic chiplet, utilizing through-silicon vias and electrical terminals, with varying configurations and redundancy to enhance performance and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processing and SRAM are integrated in existing electronic devices, then processing capability is improved, but device size and cost increase due to differing scaling rates
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by disposing SRAM chiplets on both the front and back surfaces of the processing chiplet. This dimensional change allows multiple memory layers to be stacked vertically, significantly increasing storage capacity within the same footprint area and resolving the contradiction between processing capability and device size.
Solution Approach 2:
The patent implements a nested structure where SRAM chiplets are disposed on both the front and back surfaces of the processing chiplet, with additional SRAM chiplets stacked on top of each other. This nesting approach maximizes space utilization by placing memory components in multiple layers around the central processing unit, thereby increasing storage density without proportionally increasing overall device size.
2Productivity
If more SRAM is integrated to meet performance requirements, then bandwidth is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the memory system into multiple independent SRAM chiplets that can be manufactured separately and then stacked around the processing chiplet. This segmentation allows each memory module to be optimized independently, simplifies manufacturing processes, and enables modular assembly, thereby reducing overall integration complexity while achieving high bandwidth through parallel memory access.
Solution Approach 2:
The patent creates a universal stacking architecture that can accommodate different numbers and types of SRAM chiplets on both front and back surfaces of the processing chiplet. This multi-functional platform allows the same base structure to be configured for various bandwidth requirements by simply changing the number of stacked memory layers, reducing manufacturing complexity through standardization.
3Adaptability or versatility
If traditional multi-chip module integration is used, then device functionality is achieved, but performance requirements are not met due to insufficient bandwidth
Solution Approach 1:
The patent achieves high bandwidth by transitioning from traditional two-dimensional multi-chip module layouts to three-dimensional vertical stacking. By disposing SRAM chiplets on both front and back surfaces and stacking them vertically, the system enables parallel data access through multiple memory layers, dramatically increasing bandwidth while maintaining device functionality.
Solution Approach 2:
The patent merges the processing chiplet with multiple SRAM chiplets into a single integrated three-dimensional package, combining compute and memory functions in close proximity. This merging reduces memory access latency and increases bandwidth by eliminating long external memory buses, while maintaining the versatility of having separate processing and memory components.
Data Source
AI summary
An electronic device, includes: (i) a processing chiplet configured to process data and having a first side and a second side, (ii) one or more first static random-access memory (SRAM) chiplets disposed on the first side of the processing chiplet and configured to store a first portion of the data, (iii) one or more second SRAM chiplets disposed on the second side of the processing chiplet and configured to store a second portion of the data, (iv) one or more first electrical terminals disposed on the first side of the processing chiplet and configured to electrically connect between the first side of the processing chiplet and the first SRAM chiplets, and (v) one or more second electrical terminals disposed on the second side of the processing chiplet and configured to electrically connect between the second side of the processing chiplet and the second SRAM chiplets.