3D Chiplet Stacking for Low-Latency Compute-Memory Integration
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Solution Overview
Problem
Conventional two-dimensional approaches to increasing processing power in integrated circuits are limited by size constraints, leading to inefficiencies in communication and processing capabilities.
Innovation Solution
A three-dimensional architecture for integrated circuits, where computing chiplets are stacked atop random access memory chiplets, allowing for low-latency communication and reduced area footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional processing elements are added along the width and length dimensions of the die in a two-dimensional approach, then processing power is increased, but the die area increases and is limited by size constraints
Solution Approach 1:
The patent transitions from a two-dimensional die layout to a three-dimensional stacked architecture, where multiple chiplets are vertically stacked and interconnected. This dimensional change allows processing elements to be added in the vertical direction (z-axis) rather than only in the horizontal plane, thereby increasing processing power without proportionally increasing the die area footprint.
2Productivity
If more processing elements are added to increase processing power, then computational capability improves, but communication latency increases due to larger distances between elements
Solution Approach 1:
The patent implements a hierarchical interconnection architecture where chiplets are nested in vertical stacks with multiple levels of interconnection. Local interconnects within each stack provide short-latency communication for frequently accessed data, while global interconnects handle cross-stack communication. This nested structure reduces average communication latency by providing multiple communication paths and reducing the average distance between processing elements.
3Productivity
If processing elements are distributed across a larger die area to increase capacity, then more elements can be accommodated, but power efficiency decreases due to longer signal paths
Solution Approach 1:
By stacking chiplets vertically, the patent reduces the average signal path length between processing elements and memory. In a three-dimensional stack, memory can be placed directly beneath or adjacent to processing chiplets, eliminating long horizontal signal paths. This vertical integration significantly reduces power consumption for data transfer while maintaining high processing element capacity.
Data Source
AI summary
Three-dimensional chip architecture is described herein. In one example aspect, an integrated circuit may include an interposer layer. The integrated circuit may further include a plurality of random access memory chiplets stacked atop the interposer layer, and a plurality of compute chiplets. The plurality of compute chiplets may be stacked atop a respective random access memory chip of the plurality of random access memory chiplets, such that the plurality of compute chiplets may be in electrical communication with the respective random access memory chip of the plurality of random access memory chiplets.