3D Chiplet Stacking With TSVs for Compute-in-Memory Integration
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Solution Overview
Problem
Existing two-dimensional system on chip (SoC) designs for compute-in-memory (CIM) architectures face device node mismatch challenges with non-volatile memory function blocks and control logic blocks, while three-dimensional stacked chips by microbump technology fail to meet interconnect density requirements for CIM architecture partitioning and re-integration.
Innovation Solution
A 3D chiplet architecture with a wafer-on-wafer stacked memory and control tiers, utilizing through silicon vias (TSVs) and direct/oxide bonds, along with back-end-of-line processes to create compact interconnect schemes between control logic and memory tiers, enabling integration of CMOS-compatible volatile and non-volatile memories for CIM and CNM architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two-dimensional system on chip design is used for CIM architecture, then device integration is achieved, but device node mismatch challenges occur between non-volatile memory function block and control logic block
Solution Approach 1:
The patent transitions from a two-dimensional SoC design to a three-dimensional stacked chiplet architecture. Multiple memory tiers (including NVM and volatile memory) and control logic tiers are stacked vertically and interconnected through TSVs, enabling CIM functionality while avoiding the device node mismatch problems inherent in 2D integration by separating fabrication processes into different tiers that can be optimized independently
2Productivity
If three-dimensional stacked chips by microbump technology are used, then vertical integration is achieved, but interconnect density requirements for CIM architecture partitioning and re-integration are not met
Solution Approach 1:
The architecture segments the CIM system into multiple independent tiers: NVM tiers, volatile memory tiers, and control logic tiers. Each tier can be partitioned and fabricated separately using optimized processes, then re-integrated through the interconnect fabric formed by TSVs and metal layers, achieving both vertical integration and high interconnect density
Solution Approach 2:
The patent changes the interconnection parameter from microbump technology to through-silicon via (TSV) technology with associated metal interconnect layers. This parameter change enables higher interconnect density and more flexible routing options, meeting the demands of CIM architecture partitioning and re-integration while maintaining vertical integration
3Productivity
If monolithic three-dimensional integrated circuit is used for memory architecture, then three-dimensional stacking is achieved, but feasibility for CIM and CNM architectures is limited
Solution Approach 1:
The monolithic 3DIC structure is segmented into separate chiplets that are stacked and interconnected. This includes dividing memory functions into distinct NVM and volatile memory tiers, and control logic into separate tiers, allowing each segment to be optimized for its specific function while maintaining overall CIM/CNM architecture feasibility
Solution Approach 2:
The stacked chiplet architecture provides multi-functionality by integrating both NVM and volatile memory tiers with control logic, enabling the system to support both CIM (compute-in-memory) and CNM (compute-near-memory) architectures through a single unified platform that can be configured for different computational paradigms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture achieves a low-power, high-memory capacity CIM chiplet with integrated CMOS-compatible volatile and non-volatile memories, enhancing computing efficiency and enabling integration into CPUs, GPUs, FPGAs, and AI/DNN chips for advanced dataflow and functionality.
Implementation Method 1
utilizing through silicon vias (TSVs) and direct/oxide bonds
Implementation Method 2
direct/oxide bonds
Data Source
AI summary
A semiconductor structure, includes a logic die, a memory die stack bonded to the logic die by a first oxide bond, and including a first pair of memory dies bonded together by a first direct bond, and a first through silicon via (TSV) in the logic die and extending across the first oxide bond and electrically connecting the logic die to the first pair of memory dies.