3D Chipset Hybrid Bonding for High-Density Logic-Memory Integration
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Solution Overview
Problem
Existing memory devices face challenges such as low yield, small arithmetic logic unit area, high power consumption, and the need for a large-area system-on-a-chip due to extensive input/output circuits and mesh channels, which hinder the realization of high-density memory for AI computing and high-performance computing applications.
Innovation Solution
A chipset design with multiple logic cores and memory chips bonded in a die-to-die manner using hybrid bonding, where bonding elements and input/output circuits are directly connected, reducing the need for extensive wiring and saving space, while enabling high-density memory integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large-area system on chip is used to provide more memory chips, then memory density is improved, but manufacturing yield deteriorates and area for arithmetic logic unit decreases
Solution Approach 1:
The patent divides the system into separate logic core chips and memory chips that are independently manufactured and then bonded together. This segmentation allows each chip to be optimized separately, improving manufacturing yield while achieving high memory density through 3D stacking and die-to-die bonding.
Solution Approach 2:
The patent transitions from 2D planar integration to 3D vertical stacking by bonding multiple logic core chips and memory chips in three-dimensional space. This dimensional change enables high memory density without requiring large chip area, thus improving yield while maintaining arithmetic logic unit space.
2Speed
If network-on-chip or mesh channel is used to connect memory chips, then memory bandwidth is improved, but area for arithmetic logic unit decreases due to occupation by input/output circuits and mesh channels
Solution Approach 1:
The patent moves interconnect functions from the 2D chip plane to 3D vertical space through die-to-die bonding and through-silicon vias. This enables high-bandwidth communication between logic cores and memory without consuming valuable 2D area for mesh channels or NoC infrastructure.
Solution Approach 2:
The patent introduces dedicated input/output circuits and bonding interfaces as intermediaries between logic cores and memory chips. These intermediaries handle high-bandwidth data transfer efficiently, reducing the need for extensive on-chip interconnect infrastructure and freeing up area for arithmetic logic units.
3Adaptability or versatility
If interposer layer or fan-out packaged redistribution layer is used to connect HBM and logic cores, then connectivity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the complex interposer and redistribution layer functions and replaces them with direct die-to-die bonding interfaces. This simplification reduces manufacturing complexity and cost while maintaining high connectivity between logic cores and memory through optimized bonding element arrangements.
4Adaptability or versatility
If large-area system on chip is used for connection, then connectivity capacity is improved, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by moving interconnect functions to 3D vertical stacking with short bond wires and through-silicon vias. This eliminates the need for long on-chip interconnect traces, significantly reducing resistive power losses while maintaining high connectivity capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively saves circuit wiring space, increases the number of logic cores, and achieves high-density memory, enhancing computing capability while reducing power consumption and the need for large-area connections.
Implementation Method 1
bonded in a die-to-die manner using hybrid bonding
Implementation Method 2
directly bonding the plurality of first bonding elements of the plurality of dies to the plurality of second bonding elements of the memory chip
Data Source
AI summary
The disclosure provides a chipset and a manufacturing method thereof. The chipset includes multiple logic cores and a memory chip. The logic cores respectively have a first device layer and a first substrate layer, and respectively include multiple first bonding elements and a first input/output circuit. The first bonding elements are provided in the first device layer. The first input/output circuit is provided in the first device layer. The memory chip has a second device layer and a second substrate layer, and includes second bonding elements and second input/output circuits. The second bonding elements are arranged in the second device layer. The second input/output circuits are arranged in the second device layer, and are respectively connected to the first input/output circuits of the logic cores.