3D Integrated Circuit with Hybrid Bonding for Low-Loss RF Filters
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving high performance and reduced power consumption for 5G wireless communication systems, particularly in implementing wideband filters with low insertion loss and compact designs for mobile devices.
Innovation Solution
A three-dimensional integrated circuit (3DIC) is fabricated using hybrid copper-to-copper and oxide-to-oxide bonding technology, incorporating through-alumina vias and high-performance integrated passive devices on a thin alumina ceramic substrate, which includes 2D and 3D inductors, and broadband acoustic filters, enabling efficient RF signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional semiconductor devices are used for 5G wireless communication, then device functionality is achieved, but power consumption is high and insertion loss is excessive
Solution Approach 1:
The patent transitions from conventional two-dimensional planar filters to three-dimensional vertically stacked filter structures. Multiple filter banks are stacked in the vertical dimension, enabling wider bandwidth operation and improved signal processing capability while reducing insertion loss through enhanced electromagnetic field coupling in the third dimension.
Solution Approach 2:
The patent employs composite material structures combining different dielectric materials with complementary properties. High-permittivity materials are used for capacitance enhancement while low-loss materials are used for resonator structures, achieving both compact size and low insertion loss simultaneously.
2Adaptability or versatility
If wideband filters are implemented with conventional designs, then bandwidth is increased, but device area and chip size increase
Solution Approach 1:
The patent stacks multiple filter banks vertically in the third dimension, allowing wideband operation to be achieved without proportional increases in planar chip area. The vertical stacking enables frequency multiplexing and bandwidth aggregation while maintaining a compact footprint.
Solution Approach 2:
The patent implements nested filter structures where smaller filter units are integrated within larger filter bank assemblies. Multiple resonators and capacitive elements are nested within shared structural frameworks, achieving wideband functionality with minimized component count and compact area utilization.
3Reliability
If conventional filter designs are used, then basic filtering function is achieved, but thermal performance and electrical performance are insufficient
Solution Approach 1:
The patent applies different material properties and structural configurations to specific regions of the filter assembly. High-thermal-conductivity materials are used in heat-generating areas, while low-loss dielectric materials are positioned in electromagnetic field regions. This localized optimization simultaneously improves thermal management and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced power consumption, improved thermal and electrical performance, and a compact design with reduced chip size, while also lowering costs and enabling wafer-level testing and calibration for phase array antennas.
Implementation Method 1
bonding the first oxide material to the second oxide material
Implementation Method 2
bonding at least a portion of the first plurality of pads to at least a portion of the second plurality of pads
Data Source
AI summary
A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.