3D Circuit Layout Generation via Vertical Cell Assignment
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Solution Overview
Problem
Existing software tools for 2D circuit design are not compatible with generating high-density 3D circuit designs, and developing new tools for 3D circuit design is time-consuming and costly.
Innovation Solution
A method and computing device that convert a 2D circuit layout into a 3D layout by assigning cells to multiple stacked levels and reducing rows, while maintaining a high density of interconnections, using a computing device with processors and memory to perform operations such as placement, assignment, and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing 2D circuit design tools are used, then development time and cost are reduced, but the ability to generate high-density 3D circuit designs is lost
Solution Approach 1:
The patent extends traditional 2D circuit layout tools into 3D space by introducing a vertical dimension with multiple stacked levels. Cells are assigned to different levels (e.g., level 0, level 1, level 2) and interconnected through 3D vias, transforming a planar design approach into a volumetric one while reusing the same toolchain.
Solution Approach 2:
The patent makes existing 2D layout tools universal by enabling them to handle both 2D and 3D circuit designs through a unified framework. The same placement and routing algorithms operate in 3D space, allowing a single toolset to serve multiple design dimensions without requiring separate specialized software.
2Adaptability or versatility
If new 3D circuit design tools are developed, then compatibility with 3D circuit design is improved, but development time and cost increase
Solution Approach 1:
The patent makes existing 2D layout tools universal by enabling them to handle both 2D and 3D circuit designs through a unified framework. The same placement and routing algorithms operate in 3D space, allowing a single toolset to serve multiple design dimensions without requiring separate specialized software.
Solution Approach 2:
The patent adapts 2D placement and routing algorithms to work in 3D by copying and modifying the existing 2D tool logic rather than creating entirely new 3D-specific tools. The fundamental algorithmic structure is preserved while extending its operational space to three dimensions.
3Volume of moving object
If cells are positioned on multiple stacked levels with 3D vias, then circuit compactness and performance are improved, but alignment problems occur in stacking processes
Solution Approach 1:
The patent resolves alignment issues by performing all placement and routing operations in 3D space from the beginning, rather than stacking pre-fabricated 2D layers. This volumetric approach allows precise positioning of cells and interconnections across multiple levels without requiring high-precision alignment between separately fabricated layers.
Solution Approach 2:
The patent performs preliminary 3D placement and routing before fabrication, establishing the exact three-dimensional positions of all cells and interconnections. This pre-planning in 3D space ensures that monolithic fabrication can proceed without alignment challenges, as the entire structure is defined upfront rather than assembled from stacked layers.
4Quantity of substance
If 3D circuit layouts are generated with high density, then interconnection density is improved, but wire length may increase
Solution Approach 1:
The patent utilizes the vertical dimension to reduce wire lengths by routing interconnections between cells on different levels through 3D vias. This three-dimensional routing capability allows direct vertical connections that are shorter than lateral routing paths required in 2D layouts, thereby maintaining low wire lengths while achieving high interconnection density.
Data Source
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Figure 2C~4
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AI summary
The invention concerns a method of generating, by a computing device, a 3D circuit layout based on a 2D circuit layout, the method comprising: assigning cells of first and second groups of circuit cells of the 2D circuit layout to first and second levels of the 3D circuit layout, the assignment of each circuit cell of the first and second groups being performed by: selecting, among at least one first row of a first level of the 3D circuit layout and at least one second row of a second level of the 3D circuit layout, the row having the greatest available space; and assigning the circuit cell to the selected row; and transmitting the 3D circuit layout to a manufacturing plant for fabrication.