3D Circuit Layout Mapping for Deforming Substrates
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Solution Overview
Problem
Current electronic circuit design tools face challenges in creating 3D layouts on non-planar substrates, as traditional 2D design methods fail to accurately account for material deformation and electrical property changes during 3D forming, leading to suboptimal or failed circuit performance.
Innovation Solution
An electronic arrangement and method that uses a processor to map 2D circuit designs onto substrates, accounting for elongation during 3D forming, optimizing trace thickness and electrical resistance, and providing a digital output for manufacturing equipment to ensure correct placement and functionality of circuit elements in the final 3D structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional 2D circuit design methods are used on planar substrates, then the design process is simple and familiar, but the final 3D circuit performance is suboptimal due to unaccounted material deformation and electrical property changes
Solution Approach 1:
The patent applies preliminary action by performing 3D forming simulation and calculating elongation characteristics before the actual circuit layout design. This allows the design system to pre-compensate for material deformation by adjusting trace paths and dimensions based on predicted stretch patterns, ensuring optimal circuit performance in the final 3D structure without requiring complex iterative adjustments during manufacturing
Solution Approach 2:
The patent transitions from traditional 2D circuit design to 3D-aware design by incorporating the third dimension (z-axis deformation) into the layout process. The system calculates elongation characteristics in three dimensions and uses this data to adjust circuit trace geometry, ensuring that electrical properties remain optimal after the substrate is formed into its final 3D shape
2Shape
If the substrate is formed into 3D shape after circuit placement, then the final product achieves desired complex shape, but the circuit traces experience uncontrolled elongation and resistance changes
Solution Approach 1:
The system performs preliminary 3D forming simulation to predict elongation characteristics before final circuit trace generation. By calculating the deformation field in advance, the design tool can pre-adjust trace dimensions and routing to compensate for upcoming material stretch, ensuring that electrical resistance remains within specifications after the substrate is formed into its complex 3D shape
Solution Approach 2:
The patent implements feedback by using 3D forming simulation results to iteratively optimize circuit layout parameters. The system calculates elongation characteristics, adjusts trace geometry accordingly, and re-evaluates electrical properties until optimal performance is achieved, creating a closed-loop design process that accounts for the coupling between substrate deformation and circuit performance
3Ease of operation
If 2D design tools are used for 3D target designs, then the design workflow remains simple, but the positioning of circuit elements is inaccurate on the formed substrate
Solution Approach 1:
The patent introduces an intermediary mapping layer between 2D design input and 3D substrate output. The system creates a transformation model that accounts for elongation characteristics, using this intermediary representation to accurately translate circuit element positions from the 2D design space to the final 3D substrate geometry, ensuring precise positioning without requiring designers to learn complex 3D design tools
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2~3
AI summary
An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.