3D Integrated Circuit Structure With Metal-Filled Via
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Solution Overview
Problem
The existing 3D integrated circuit technology faces challenges in achieving high device density and reducing wire length and via numbers due to physical limitations in two-dimensional integration, particularly in aligning and forming through silicon vias in the through-silicon-last process.
Innovation Solution
A 3D integrated circuit structure is formed by aligning connection pads on two semiconductor wafers and using a metal-filled via that narrows in the center, extending through both wafers, with an insulative spacer, to simultaneously connect pads and reduce wire length and via numbers, improving connectivity and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional integration is used to increase device density, then more components can be integrated into a given area, but the minimum feature size limit and increased interconnection complexity become constraints
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple semiconductor wafers. This dimensional change allows continued increase in device density without further reducing minimum feature size, as devices are arranged in vertical layers rather than only in-plane. The through-silicon vias enable interconnections between stacked wafers, maintaining manageable interconnection complexity while achieving higher overall integration density.
2Quantity of substance
If more devices are put into one chip to increase integration density, then more components are integrated, but the number and length of interconnections increase causing higher RC delay and power consumption
Solution Approach 1:
By stacking wafers vertically and using through-silicon vias for interconnections, the patent reduces the horizontal wire length required to connect devices. The vertical via paths are significantly shorter than equivalent horizontal routing paths in planar designs, reducing both RC delay and power consumption while maintaining high integration density.
3Reliability
If through silicon vias are formed in the through-silicon-last process, then alignment between wafers is required, but achieving precise alignment and via formation becomes challenging
Solution Approach 1:
The patent forms through-silicon vias in the lower wafer before wafer bonding (through-silicon-first approach), rather than after bonding. This preliminary action allows via formation and filling to be performed when the wafer is accessible from both sides, enabling better alignment control and precision. After via formation, the wafers are then bonded, ensuring reliable connectivity while achieving the required alignment precision during the via formation process.
Data Source
AI summary
A structure of connecting at least two integrated circuits in a 3D arrangement by a metal-filled through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.