3D Circuit Mounting Structures for Dense Chip Packaging and Heat Dissipation
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Solution Overview
Problem
Traditional 2D chip packaging processes limit circuit density and suffer from inefficient heat dissipation, leading to excessive heating in certain regions.
Innovation Solution
Implementing a three-dimensional (3D) chip package layout using triangular prism or rectangular mounting structures, which allow for higher transistor density and improved heat dissipation by utilizing novel internal trace routes and heat sink designs that encompass multiple surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a traditional 2D chip package layout is used, then the manufacturing process is simple, but the circuit density per unit area is limited
Solution Approach 1:
The patent transitions from a traditional 2D chip package layout to a 3D mounting structure, utilizing vertical space to mount chip packages on multiple surfaces (top, bottom, and side faces) of a substrate. This dimensional change increases the number of transistors per unit area by distributing chip packages across three-dimensional space rather than confining them to a single plane, thereby resolving the contradiction between manufacturing simplicity and circuit density.
2Device complexity
If a traditional 2D chip package layout is used, then the structure is simple, but heat dissipation is inefficient
Solution Approach 1:
The patent introduces a 3D mounting structure with chip packages distributed across multiple surfaces at different heights, creating enhanced heat dissipation pathways. The vertical arrangement allows heat to dissipate in multiple directions (upward from top-mounted packages, downward from bottom-mounted packages, and laterally from side-mounted packages) rather than being confined to a single plane, thereby improving heat dissipation efficiency while accepting increased structural complexity.
Solution Approach 2:
The patent divides the chip package mounting into multiple segmented locations across different surfaces of the substrate (top face, bottom face, side faces). This segmentation distributes heat-generating components throughout the 3D structure, preventing heat concentration in a single region and enabling more effective thermal management through distributed heat sources and multiple dissipation pathways.
3Ease of manufacture
If chip packages are mounted in a 2D array on the substrate, then the manufacturing process is straightforward, but the number of transistors per unit area is limited
Solution Approach 1:
The patent employs a 3D mounting structure that extends vertically from the substrate, allowing chip packages to be mounted on the top face, bottom face, and side faces. This three-dimensional arrangement multiplies the available mounting surfaces from a single 2D plane to multiple surfaces at different elevations, thereby increasing the total number of transistors per unit area while maintaining a manufacturing process that builds upon traditional techniques.
4Device complexity
If heat is dissipated primarily from the top of the chip package, then the heat sink design is simple, but heat becomes trapped and builds up between the chip package and base board
Solution Approach 1:
The patent transitions from a single-direction (top-only) heat dissipation approach to a multi-directional heat dissipation system enabled by the 3D mounting structure. Chip packages mounted on different surfaces (top, bottom, sides) dissipate heat in multiple directions simultaneously, creating thermal pathways that prevent heat trapping between the chip package and base board. This resolves the contradiction by accepting more complex heat sink designs that accommodate multi-surface mounting and multi-directional heat flow.
Solution Approach 2:
The patent segments the heat dissipation function across multiple chip package locations on different surfaces of the 3D structure. Instead of relying on a single heat sink at the top, heat is dissipated from multiple distributed locations (top-mounted packages, bottom-mounted packages, side-mounted packages), creating multiple independent thermal pathways that prevent heat accumulation in any single region, particularly in the ball grid array region.
Data Source
AI summary
A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.