3D Integrated Circuit Placement and Routing Optimization
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Solution Overview
Problem
Current CAD tools face challenges in optimizing the design of monolithic three-dimensional integrated circuits, particularly in minimizing the number of Through-Silicon Vias (TSVs) and leveraging dense inter-layer connectivity to optimize object placement across layers with disparate characteristics in a 3D space.
Innovation Solution
The method involves using 2D CAD tools for placement and routing in a monolithic 3D manufacturing process, partitioning designs into strata with distinct characteristics, and optimizing placement and routing to maximize physical proximity and connectivity between layers, leveraging the dense inter-layer connectivity of monolithic 3D technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Through-Silicon Vias (TSVs) are used to connect stacked layers, then inter-layer connectivity is achieved, but the number of TSVs increases device complexity and manufacturing difficulty
Solution Approach 1:
The patent extracts and removes TSVs from the design by redistributing logic functions to adjacent layers, eliminating the need for vertical through-silicon connections and simplifying the device structure
Solution Approach 2:
The patent transitions from vertical 3D stacking with TSVs to a approach that leverages lateral connectivity and in-layer routing, changing the dimensional strategy for achieving connectivity
2Adaptability or versatility
If TSVs are used for inter-layer connection, then layers are connected, but manufacturing becomes more difficult and expensive
Solution Approach 1:
The patent removes TSVs from the manufacturing process entirely by redesigning the architecture to achieve connectivity through lateral routing and logic redistribution on adjacent layers, eliminating the complex TSV fabrication steps
Solution Approach 2:
The patent replaces expensive, complex TSV structures with simpler, more manufacturable routing structures that can be formed using standard semiconductor fabrication processes
3Ease of operation
If CAD tools are designed for planar 2D layouts, then design simplicity is maintained, but optimization for 3D monolithic structures with dense inter-layer connectivity is limited
Solution Approach 1:
The patent segments the design into distinct strata with specific characteristics, allowing separate optimization of each layer while maintaining overall 3D connectivity through logical partitioning
Solution Approach 2:
The patent extends traditional 2D CAD tool capabilities into the third dimension by implementing multi-strata partitioning and placement algorithms that optimize object distribution across vertical layers while leveraging dense inter-layer connectivity
Data Source
AI summary
A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level; levels connection pads between the first level and the second level; providing placement data of the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the placement of the levels connection pads, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool, where at least one metal routing layer is in-between the first level first transistors and the second level second transistors.