3D Integrated Circuit Stacking With Redistributed Bonding Pads
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Solution Overview
Problem
Current three-dimensional integrated circuit technologies face challenges in die bonding pad position, size, and quantity limitations, which hinder efficient stacking and interconnection of semiconductor structures, limiting the potential for higher performance and density.
Innovation Solution
A three-dimensional integrated circuit structure is developed using a hybrid bonding method that stacks semiconductor structures with re-distribution layers, allowing direct bonding of copper pads and insulating layers, and incorporating through-silicon vias and conductive posts for enhanced electrical connectivity, along with solder bumps for interconnection, to overcome the limitations of traditional bonding methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional die bonding methods are used, then bonding pad positions and sizes are fixed by manufacturing constraints, but this limits the flexibility and density of 3D integration stacking
Solution Approach 1:
The patent introduces re-distribution layers that redistribute bonding pads in the lateral dimension, allowing bonding pads to be positioned flexibly on the chip surface while maintaining electrical connectivity to underlying dies through vertical vias. This dimensional redistribution resolves the contradiction between bonding pad position flexibility and manufacturing constraints.
Solution Approach 2:
The bonding interface is segmented into multiple re-distribution layers, each capable of independent pad positioning and routing. This segmentation allows the bonding pad array to be reconfigured across multiple layers, providing flexibility in pad placement without requiring complete redesign of the entire bonding interface.
2Quantity of substance
If the number of bonding pads is increased to improve connectivity, then more dies can be interconnected, but the area occupied by bonding pads increases reducing chip density
Solution Approach 1:
The patent utilizes vertical stacking of multiple re-distribution layers to increase the effective number of bonding pads without proportionally increasing the lateral chip area. By distributing pads across multiple vertical layers, the system achieves higher connectivity density while maintaining compact footprints.
Solution Approach 2:
Multiple re-distribution layers are nested vertically, with each layer containing bonding pads and interconnect structures. This nesting allows numerous bonding pads to be packed into a compact vertical volume, increasing the quantity of pads without linearly increasing the horizontal area occupation.
3Adaptability or versatility
If heterogeneous integration of different technologies is implemented, then functionality and performance are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
Re-distribution layers serve as intermediary structures between heterogeneous dies with different pad configurations. These intermediate layers provide buffer zones for alignment compensation and signal routing, allowing dies from different manufacturing processes to be integrated with relaxed precision requirements.
Solution Approach 2:
The re-distribution layers enable parameter changes in bonding pad positions, sizes, and spacing between adjacent dies. By decoupling the pad parameters of different dies through intermediate routing layers, the system can integrate heterogeneous technologies with different geometric parameters without requiring ultra-precise alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more flexible and efficient stacking of semiconductor structures, improving performance, density, and functionality while reducing form factor and costs, by allowing for redefinition of bonding pad positions and increased connectivity options.
Implementation Method 1
A first semiconductor structure is hybrid bonded to a second semiconductor structure. The plurality of first bonding pads is directly bonded to the plurality of second bonding pads, respectively.
Implementation Method 2
The first insulating layer is directly bonded to the second insulating layer.
Implementation Method 3
The plurality of connecting elements comprises solder bumps or solder balls.
Implementation Method 4
The TSV die comprises a plurality of through-silicon vias for electrically connecting the second re-distribution layer with the third re-distribution layer.
Data Source
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AI summary
The present invention provides a 3D integrated circuit structure formed by stacking semiconductor structures. The semiconductor structures form a multi-die heterogeneous 3D packaging by direct bonding the bonding pads of re-distribution layers. The same or different dies are used to produce the semiconductor structures through the back-end packaging process, and then hybrid bonding technology is used to stack and interconnect the semiconductor structures. The position of the bonding pad can be redefined by re-distribution layer, thereby overcoming the limitations of chip bonding pad position, chip size and quantity.