3D Circuit Architecture Spatial Alignment Matrix Multiplication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computing devices face challenges in achieving efficient memory storage and matrix multiplication operations, particularly due to the need for software-based transpose operations and high data movement requirements.
Innovation Solution
The implementation of a 3D circuit architecture that allows for spatial alignment of data tiers, enabling a "free" matrix transpose in hardware and minimizing data movement through 3D connections and in-place matrix multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is streamed from memory devices through a processing element array for matrix multiplication, then computation can be performed, but the data in the second matrix requires column-wise reading which necessitates a transpose operation in software, increasing complexity and time
Solution Approach 1:
The patent introduces a third dimension (vertical stacking of tiers) to resolve the transpose operation bottleneck. By organizing data tiers vertically in 3D space, the system enables direct column-wise access without requiring software-based transposition, thus eliminating the time loss associated with transpose operations while maintaining computational productivity
2Device complexity
If data tiers are arranged in traditional 2D layout, then circuit design is simpler, but data movement requirements increase for matrix operations
Solution Approach 1:
The patent transitions from 2D to 3D data tier arrangement, adding a vertical dimension to the circuit architecture. This 3D configuration reduces data movement volume by enabling direct spatial alignment between data tiers, allowing matrix operations to access data more efficiently without requiring extensive data shuffling across the circuit
3Loss of time
If spatial alignment of data tiers is implemented, then data movement is minimized and matrix transpose is achieved in hardware, but the device complexity increases due to 3D architecture requirements
Solution Approach 1:
The patent implements spatial alignment by stacking data tiers vertically in 3D space, which enables hardware-based transpose operations through direct column-wise access. While this reduces transpose operation time significantly, it does increase device complexity due to the requirements of 3D integration and alignment mechanisms
Data Source
AI summary
According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.