3D Circuit Structure Reducing Line Width and Resistance
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Solution Overview
Problem
In display technology, reducing the size of pixel units to increase resolution is hindered by the inability to minimize metal wire size due to resistance issues, leading to reduced aperture ratios and potential substrate deformation from increased wire thickness.
Innovation Solution
A three-dimension circuit structure is designed with a substrate featuring a cavity, a first conductive layer covering the cavity's inside walls, and a filled material that differs from the conductive layers, allowing for a compact layout and reduced line width by utilizing the cavity to save layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of metal wire is reduced to fit reduced-size pixel units, then the layout area is saved, but the resistance increases
Solution Approach 1:
The patent transitions from planar (2D) metal wire layout to three-dimensional (3D) conductive structure by forming conductive layers that extend vertically into the substrate. The first conductive layer is formed in a cavity and extends to the front surface, while the second conductive layer is formed over it, creating a stacked 3D configuration that reduces lateral footprint while maintaining conductive performance.
Solution Approach 2:
The patent implements nesting by placing the first conductive layer inside a cavity formed in the substrate, then embedding it within the second conductive layer. This nested arrangement allows multiple conductive elements to occupy overlapping spatial regions, effectively reducing the overall layout area while preserving electrical connectivity.
2Reliability
If the thickness of metal wire is increased to reduce resistance, then the resistance is reduced, but the substrate may be deformed
Solution Approach 1:
Instead of increasing metal wire thickness in the lateral plane, the patent utilizes the vertical dimension by forming conductive layers that extend into the substrate cavity. This 3D approach distributes the conductive material volume vertically rather than laterally, achieving low resistance without increasing surface footprint or causing substrate deformation.
Solution Approach 2:
The patent applies local quality by concentrating conductive material specifically in the cavity region where it is most needed for electrical connectivity, rather than uniformly increasing metal wire thickness across the entire pixel unit. This localized approach reduces resistance where critical while maintaining substrate stability elsewhere.
3Reliability
If the thickness of metal wire is increased to reduce resistance, then the resistance is reduced, but the process complexity increases
Solution Approach 1:
The patent segments the conductive structure into multiple distinct layers: the first conductive layer formed in the cavity, and the second conductive layer formed over it. This segmentation allows each layer to be optimized independently for its specific function, achieving low resistance through cumulative cross-sectional area while maintaining processability through standardized layer-by-layer fabrication.
Data Source
AI summary
A three-dimension circuit structure includes a substrate, a first conductive layer, a filled material and a second conductive layer. The substrate has an upper surface and a cavity located at the upper surface. The first conductive layer covers the inside walls of the cavity and protrudes out the upper surface. The filled material fills the cavity and covers the first conductive layer. The second conductive layer covers the filled material and a portion of the first conductive layer, and the first conductive layer and the second conductive layer encapsulate the filled material. The material of the filled material is different from that of the first conductive layer and the second conductive layer.