3D Circuit Z-Axis Interconnects for High Density Stacking
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Solution Overview
Problem
The limitations of Moore's Law, which predicts a doubling of transistors on IC dies every two years, are nearing an end as the maximum number of transistors that can be defined on a semiconductor substrate is reached, necessitating alternative advancements to increase transistor density.
Innovation Solution
A three-dimensional (3D) circuit is formed by vertically stacking two or more integrated circuit (IC) dies to partially overlap, with circuit blocks on each die overlapping and electrically connecting through z-axis wiring that crosses bonding layers, allowing for increased transistor density and improved signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar IC fabrication is used, then manufacturing process is simple, but transistor density reaches maximum limit
Solution Approach 1:
The patent transitions from traditional two-dimensional planar IC fabrication to three-dimensional stacked die architecture. Multiple IC dies are stacked vertically and bonded together, with circuit blocks on different dies overlapping in the vertical dimension. This enables significantly higher transistor density by utilizing the z-axis direction, effectively moving from a 2D to 3D space utilization model while maintaining compatibility with existing fabrication processes.
2Productivity
If transistor density is increased on a single die, then processing capacity improves, but wire length and power consumption increase
Solution Approach 1:
The patent stacks multiple IC dies vertically, allowing circuit blocks to be positioned in the vertical dimension rather than spread out horizontally. This reduces the physical distance between connected components from millimeter-scale planar distances to micrometer-scale vertical distances through short z-axis interconnects, thereby reducing power consumption while maintaining high processing capacity.
Solution Approach 2:
The patent implements nested overlapping regions where circuit blocks on upper dies are positioned directly above corresponding circuit blocks on lower dies. This nesting arrangement creates vertical alignment and overlap zones that enable direct short-distance connections between stacked circuit blocks, reducing wire length and associated power consumption while preserving functional processing capacity.
3Adaptability or versatility
If more circuit blocks are placed on a single die, then functionality increases, but manufacturing precision requirements exceed current capabilities
Solution Approach 1:
The patent divides a complex high-functionality circuit system into multiple separate IC dies, each containing a subset of circuit blocks. These segmented dies are manufactured using existing precision-capable fabrication processes, then stacked and bonded together. This segmentation allows each individual die to be manufactured within current precision limits while the stacked assembly achieves the overall high functionality that would be impossible on a single die.
Solution Approach 2:
The patent distributes circuit blocks across multiple dies stacked in the vertical dimension rather than concentrating all functionality on a single die. This spatial distribution in the z-axis direction allows the system to achieve high overall functionality while each individual die maintains manageable complexity and manufacturing precision requirements consistent with current fabrication capabilities.
Data Source
AI summary
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.