3D IC Clock Network Synchronization via Buffer Input Shorting
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Solution Overview
Problem
Synchronizing global clocks in 3D stacks of integrated circuits is challenging due to constraints such as strata testability at target clock frequency, low power and area overheads, robustness to variations, and compatibility with voltage and frequency scaling, while maintaining low inter-stratum and within-stratum skews.
Innovation Solution
A clock distribution network with a multiple-level buffered clock tree and multiplexers is implemented, where inputs of clock buffers on each stratum are shorted using chip-to-chip interconnects to reduce global clock skew, and a master stratum drives non-master strata to maintain uniform clock frequency and reduce skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional clock distribution networks are used in 3D stacks, then each stratum can be tested independently before stacking, but inter-stratum clock skew increases significantly
Solution Approach 1:
The patent merges the clock distribution networks of multiple strata by shorting corresponding clock buffer inputs across strata using TSVs. This creates a unified clock distribution system where clock buffers on different strata share common inputs, ensuring synchronized clock signals and reducing inter-stratum skew while maintaining individual stratum testability through the selective activation of clock sources.
Solution Approach 2:
The patent introduces TSVs (through-silicon vias) as intermediary connections between strata to short clock buffer inputs. These TSVs act as mediators that physically connect corresponding clock buffers across different strata, enabling the shorting of clock inputs without requiring direct physical contact between strata and maintaining electrical isolation during individual stratum testing.
2Manufacturing precision
If clock inputs are shorted across strata to reduce skew, then clock synchronization improves, but power consumption and area overhead increase
Solution Approach 1:
The patent applies partial shorting of clock inputs by selectively connecting only certain clock buffers across strata using TSVs. Not all clock buffers are shorted, but only those necessary to achieve adequate skew reduction. This partial action approach reduces power consumption and area overhead compared to complete shorting of all clock inputs, while still achieving the desired clock synchronization.
3Manufacturing precision
If multiple TSVs are used to short clock inputs across strata, then clock skew is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies local quality by selectively shorting clock inputs only in specific locations where skew reduction is most critical. Instead of uniformly shorting all clock inputs across the entire 3D stack, the invention identifies and shorts only the necessary clock buffers in strategic locations, reducing the total number of TSVs required while maintaining effective clock synchronization.
4Manufacturing precision
If a unified clock distribution network is implemented across all strata, then clock skew is minimized, but adaptability to voltage and frequency scaling is reduced
Solution Approach 1:
The patent introduces dynamic configurability to the clock distribution network by implementing selectable clock sources and controllable switching mechanisms. This allows the system to dynamically adjust between unified and independent clock distribution modes, enabling voltage and frequency scaling operations while maintaining the option for clock input shorting when skew reduction is required. The dynamic architecture adapts to different operational requirements.
Data Source
AI summary
There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.