3D CMOS Image Sensor Fin Layout for Smaller Pixels
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Solution Overview
Problem
Current planar BSI CMOS image sensors face challenges in miniaturizing pixel size without compromising full well capacity and fill factor, as regions of photodiodes and active areas like sources and drains occupy the same substrate plane, limiting device density and photosensitive performance.
Innovation Solution
A 3D CMOS image sensor structure is developed where the photodiode is formed vertically protruding from the substrate surface to connect with the source node of the transistor, allowing channels and isolation structures to be placed on the photodiode layout area, reducing layout space and crosstalk through a shallow trench isolation layer and fin structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photodiode and transistor regions occupy the same substrate plane in planar BSI image sensor, then manufacturing is simplified, but layout area increases and pixel size cannot be miniaturized
Solution Approach 1:
The patent transitions from a planar 2D architecture to a 3D vertical architecture by forming a fin structure that protrudes from the substrate surface. The photodiode is positioned at the base of the fin while transistor regions are formed on the fin structure, utilizing the vertical dimension to reduce lateral layout area. This dimensional change allows both photodiode and transistor regions to coexist in a compact footprint without increasing the overall pixel area.
Solution Approach 2:
The fin structure serves as a nested configuration where the photodiode region is embedded at the base and transistor regions are formed on the protruding fin portion. This nesting approach allows multiple functional regions to be packed vertically within a single lateral footprint, effectively reducing the layout area while maintaining all necessary functional components.
2Quantity of substance
If photodiode and transistor regions occupy the same substrate plane, then device density is reduced, but crosstalk between photoelectric signals increases
Solution Approach 1:
By transitioning to a 3D vertical architecture with the fin structure, the patent separates photodiode and transistor regions along the vertical dimension rather than confining them to the same lateral plane. This spatial separation in the vertical dimension reduces lateral crosstalk between photoelectric signals and transistor regions, while the fin structure maintains high device density through compact vertical integration.
3Area of stationary object
If pixel size is miniaturized without improving architecture, then layout area decreases, but full well capacity and fill factor are compromised
Solution Approach 1:
The patent achieves pixel size miniaturization by utilizing the vertical dimension through the fin structure. The photodiode is positioned at the base of the fin while transistor regions occupy the fin portion, allowing compact lateral footprint. The vertical fin structure provides sufficient active area for maintaining full well capacity and fill factor despite the reduced lateral pixel dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces pixel size while maintaining full well capacity and fill factor, enhancing device density and photosensitive performance by minimizing layout area and crosstalk between photoelectric signals.
Implementation Method 1
Each pixel includes transistors, capacitors and photodiodes, wherein electrical energy is induced in the photodiode upon exposure to the luminous environment. Each pixel generates electrons proportional to an amount of light entering the pixel.
Data Source
AI summary
A 3D CMOS image sensor is provided in the present invention, including a semiconductor substrate, a photodiode and a well formed in the semiconductor substrate, a shallow trench isolation (STI) layer formed on a front surface of the semiconductor substrate, a fin protruding upwardly from the semiconductor substrate through the STI layer, wherein the fin is composed of the photodiode and the well, a first gate spanning the photodiode portion and the well portion abutting the photodiode portion of the fin to constitute a transfer transistor, a second gate spanning in the middle of the well portion of the fin to constitute a reset transistor, and a floating diffusion region in the well portion of the fin between the first gate and the second gate electrically connecting the transfer transistor and the reset transistor.