3D CMOS Logic Layout With Self-Aligned Vertical Channel Transistors
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to overcome scaling limitations in two-dimensional (2D) circuits and achieve higher transistor density, which is difficult to achieve in three-dimensional (3D) integration, especially for logic chips where traditional 3D NAND flash memory techniques are not directly applicable.
Innovation Solution
The method involves forming a layer stack with a metal layer between dielectric layers to create precision gate electrodes that are self-aligned to the channel, enabling efficient formation of aligned 3D metal stacks and routing, and allowing for multiple threshold voltage transistors with advanced 3D CMOS metals that can withstand high temperatures, facilitating the growth of vertical channel structures for transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D circuit fabrication is used, then manufacturing process is simple, but transistor density is limited
Solution Approach 1:
The patent transitions from traditional 2D planar transistor fabrication to 3D vertical channel transistor fabrication. The vertical channel structures extend perpendicular to the substrate surface, utilizing the third dimension to increase transistor density without proportionally increasing footprint area. This dimensional change enables higher packing density while managing fabrication complexity through self-aligned processes.
2Quantity of substance
If 3D vertical channel transistors are formed, then transistor density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication processes where the vertical channel structures are automatically positioned relative to gate electrodes and other features through conformal deposition and etch processes. The spacer layers and epitaxial growth steps create self-aligned features without requiring additional alignment steps, thereby maintaining manufacturing precision while enabling 3D vertical channel transistor formation for increased density.
3Manufacturing precision
If advanced 3D CMOS metals are used, then gate electrode precision improves, but process temperature requirements increase
Solution Approach 1:
The patent utilizes advanced 3D CMOS metal materials with modified physical and chemical properties that enable precise gate electrode formation at elevated temperatures. The metal layer composition and structure are optimized to withstand higher process temperatures while maintaining dimensional precision and electrical performance. This parameter change in material properties allows simultaneous achievement of high precision and temperature resilience.
4Reliability
If vertical channel structures are epitaxially grown, then transistor control over short channel effects improves, but fabrication process steps increase
Solution Approach 1:
The patent implements preliminary preparation steps including substrate conditioning, nucleation layer formation, and template structure creation before the epitaxial growth of vertical channel structures. These preliminary actions ensure that the subsequent epitaxial process proceeds uniformly and achieves the desired vertical channel morphology with excellent short channel effect control. By preparing the substrate and template structures in advance, the overall fabrication process is streamlined despite the added complexity of epitaxial growth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased transistor density by allowing for 3D vertical channel transistors with improved control over short channel effects, compatibility with existing logic circuit layouts, and more efficient metal gate electrode processing, leading to enhanced circuit packing density and performance.
Implementation Method 1
forming a layer stack on a substrate, the layer stack having a metal layer of a first metal positioned between a first dielectric layer and a second dielectric layer
Implementation Method 2
epitaxially growing vertical channel structures in the openings for channels of transistors
Data Source
AI summary
Aspects of the present disclosure provide a 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including sidewall structures of a first gate metal sandwiched by dielectric layers, a first epitaxially grown channel surrounded by the sidewall structures; a second semiconductor device formed on the same substrate adjacent to the first semiconductor device that includes sidewall structures of a second gate metal sandwiched by dielectric layers, a second epitaxially grown channel surrounded by the sidewall structures; a salicide layer formed between the first and second semiconductor devices and metallization contacting each of the S/D regions and the gate regions. The 3D semiconductor apparatus may include a P+ epitaxially grown channel formed on the same substrate adjacent to an N+ epitaxially grown channel, the P+ epitaxially grown channel separated from N+ epitaxially grown channel by a diffusion break.