3D CMOS Stacked Nano-Sheets for Transistor Density
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Solution Overview
Problem
As semiconductor devices approach single-digit nanometer fabrication nodes, two-dimensional transistor scaling faces challenges due to manufacturing variability and electrostatic limitations, leading to saturation in critical dimension scaling, and resistance and reliability concerns that limit transistor density and wiring efficiency in traditional 2D circuits.
Innovation Solution
The development of 3D CMOS devices using stacked nano-sheets with germanium or SiGe on silicon substrates, allowing for increased transistor density by forming NMOS and PMOS regions on separate substrates and combining them with a new metal X routing layer, enabling high mobility and reduced silicon area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D transistor scaling is continued, then transistor density per unit area increases, but manufacturing variability and electrostatic limitations cause critical dimension scaling to saturate
Solution Approach 1:
The patent transitions from 2D planar transistor layout to 3D vertical stacking architecture. Multiple transistor layers are stacked vertically above each other on the same substrate footprint, transforming the scaling dimension from two-dimensional (area) to three-dimensional (volume). This enables continued transistor density improvement without further reducing critical dimensions, thereby avoiding manufacturing precision saturation while achieving higher device counts per chip area.
2Quantity of substance
If wire pitch scaling is reduced to improve transistor density, then resistance and capacitance increase, but reliability concerns limit further scaling
Solution Approach 1:
The 3D vertical stacking architecture provides dedicated vertical interconnect paths through the stacked layers, separating wire routing from the horizontal plane. This vertical dimension for interconnection allows wire pitch to be maintained at reliable dimensions while achieving high transistor density through vertical stacking, thereby decoupling the trade-off between density and reliability that constrained 2D scaling.
3Quantity of substance
If 3D integration is implemented, then transistor density in volume increases, but device complexity and fabrication process complexity increase
Solution Approach 1:
The fabrication process is segmented into distinct modular stages: forming first transistor layers, depositing interlayer dielectric, creating vias, depositing metal interconnects, and stacking subsequent transistor layers. Each stage is independently processable and can be optimized separately. This segmentation transforms the complex 3D fabrication into a sequence of manageable 2D-like processing steps, reducing overall process complexity while achieving 3D integration.
Solution Approach 2:
Transistor layers are fabricated completely on separate substrates before bonding them together in the desired stacked configuration. This preliminary fabrication allows each layer to be optimized independently using standard 2D CMOS processes, avoiding the need to develop entirely new 3D fabrication techniques. The pre-fabricated layers are then bonded with aligned interconnects, simplifying the integration process.
Data Source
AI summary
A semiconductor device includes an NMOS device formed on a first substrate bonded with a second substrate having a PMOS device formed thereon, with the bonding achieved by contacting a first wiring layer formed on the NMOS device with a second wiring layer formed on the PMOS device.