3D CMOS Staircase Interconnect Architecture for Higher Transistor Density
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the inefficiency of existing 3D integration technologies for scaling transistors, which limits transistor density and wiring complexity, making it difficult to continue scaling beyond single-digit nanometer nodes due to manufacturing variability and electrostatic device limitations.
Innovation Solution
The implementation of a monolithically integrated 3D CMOS device architecture with a generic device stack and customization layers, where all CFET source, drain, and gate connections are wired to an array of contacts above the top CMOS level, enabling efficient stacking and routing of transistors with a staircase configuration and vertical contacts for improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D transistor scaling is used to increase transistor density, then transistor density per unit area increases, but manufacturing variability and electrostatic device limitations prevent further scaling beyond single-digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar transistor scaling to 3D vertical stacking of transistors. Multiple transistor layers are stacked vertically with shared gates, enabling continued density improvement by utilizing the third dimension (vertical space) rather than further compressing horizontal dimensions where manufacturing variability becomes prohibitive.
2Quantity of substance
If 3D integration is used to increase transistor density, then transistor density in volume increases, but wiring complexity and routing congestion increase
Solution Approach 1:
The patent introduces vertical interconnects that pass through multiple transistor layers to access drains and sources, enabling wiring to occur in the vertical dimension. This reduces planar routing congestion by utilizing the third dimension for interconnections, thereby decreasing overall wiring complexity despite the 3D transistor stacking.
3Productivity
If transistors are stacked vertically in 3D configuration, then area scaling efficiency improves, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the manufacturing process into distinct segmentation stages: forming alternating n-type and p-type transistor layers, creating shared gates between layers, and establishing vertical interconnects. This segmentation of the complex 3D manufacturing process into manageable sequential steps reduces overall manufacturing process complexity while achieving area scaling efficiency.
Solution Approach 2:
The patent merges multiple transistor layers to share common gates, reducing the total number of gates that need to be manufactured and controlled. This merging of functions across vertical layers simplifies the manufacturing process by reducing redundant structures while maintaining high area scaling efficiency.
Data Source
AI summary
In a method of forming a semiconductor device, a plurality of transistor pairs is formed to be stacked over a substrate. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. A sequence of vertical and lateral etch steps are performed to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.