3D CMOS Vertical Transistor Stacking Without Thermal Damage
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Solution Overview
Problem
The use of vertical transistors in CMOS integrated circuits is hindered by their low driving capability and the predominance of n-type transistors, making them impractical for high-performance applications, particularly in advanced technology nodes requiring EUV lithography.
Innovation Solution
Constructing 3D CMOS ICs with vertical transistors of different types in separate levels, using single-crystalline semiconductor layers, and employing gate extensions to facilitate coupling between transistors, while avoiding high-temperature dopant activation that could damage underlying circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vertical transistors are constructed using polycrystalline or amorphous semiconductor layers, then the manufacturing process is simpler and can be performed at lower temperatures, but the carrier mobility is low and leakage is high
Solution Approach 1:
The patent applies preliminary action by forming and doping the semiconductor layer with desired crystalline structure and dopant distribution BEFORE transferring it to the final substrate. This allows the semiconductor to achieve optimal electrical properties in a controlled environment, then be transferred as a completed component rather than attempting to form the crystalline structure after substrate integration, which would require damaging high temperatures.
Solution Approach 2:
The patent uses a sacrificial layer as an intermediary during the transfer process. The sacrificial layer temporarily supports the semiconductor structure during fabrication and transfer, then is selectively removed to release the pre-formed crystalline semiconductor onto the final substrate without requiring high-temperature processing on the substrate.
2Reliability
If dopant activation is performed after transferring single-crystalline semiconductor to the substrate, then the semiconductor can be properly doped, but the high temperature required would damage underlying interconnects and circuits
Solution Approach 1:
The patent performs dopant activation in the donor substrate BEFORE transferring the semiconductor layer to the final substrate. This preliminary doping and activation occurs in a controlled environment where high temperatures can be applied without damaging sensitive interconnects, as the semiconductor is still supported by the robust donor substrate capable of withstanding thermal processing.
Solution Approach 2:
The patent inverts the conventional sequence by doping and activating the semiconductor layer while it is still attached to the donor substrate, then transferring the already-doped layer to the final substrate. This reverses the traditional approach of transferring first then doping, allowing thermal processing to occur on the donor substrate rather than the final device substrate, thereby avoiding thermal damage to completed circuits.
3Ease of manufacture
If only n-type vertical transistors are used, then the manufacturing process is simplified, but the device cannot function as a CMOS logic circuit requiring both n-type and p-type transistors
Solution Approach 1:
The patent segments the CMOS implementation into separate donor substrates for n-type and p-type vertical transistors. Each donor substrate is independently prepared and processed, allowing optimization for each transistor type without interference. The segmented transistors are then integrated on the final substrate to create functional CMOS logic circuits, combining the benefits of simplified individual fabrication with full CMOS functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-performance 3D CMOS ICs with reduced parasitic capacitance and high carrier mobility, overcoming the limitations of conventional vertical transistors and enabling their use in both memory and logic circuits.
Implementation Method 1
vertical transistors constructed from a single-crystalline semiconductor layer disposed above a substrate which has circuits comprising planar transistors
Implementation Method 2
A gate extension mask is patterned over a region that touches or encompasses the vertical transistor in question
Implementation Method 3
The sacrificial dielectric is etched, preferably partly, with the gate-extension mask at a first etch step... the sacrificial dielectric is blanket-etched in a second etch step... The so-patterned sacrificial dielectric acts as a mask for the anisotropic etching of the gate material
Implementation Method 4
This is to dope the vertical transistors and activate the dopants before transferring a single-crystalline semiconductor over the substrate
Data Source
AI summary
Disclosed are novel structures and methods for 3D CMOS integrated circuits built with vertical transistors. A gate extension is selectively patterned by first patterning a sacrificial dielectric disposed on a gate material. A 3D CMOS IC comprises vertical transistors of one type constructed in one level and those of an opposite type in another level. The gate of lower-level vertical transistors may be coupled to a top interconnect directly through a 3D gate contact or indirectly through an upper-level via and a lower-level contact. A common-gate coupling may be formed between vertical transistors in different levels through a strapping contact or a gate via. A common-drain coupling may be formed between vertical transistors in different levels by forming upper-level vertical transistor on a piece of conductive film disposed over lower-level vertical transistor with or without an intervening top contact for lower-level vertical transistor.