3D Compute Circuit with High-Density Z-Axis Interconnects
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Solution Overview
Problem
The end of Moore's law has been reached, limiting the number of transistors that can be defined on a semiconductor substrate, necessitating new approaches to increase transistor density in IC chips.
Innovation Solution
A 3D circuit is formed by vertically stacking IC dies to allow circuit blocks to overlap and connect through z-axis wiring, utilizing direct bonding techniques like DBI to establish short, high-density connections between interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more transistors are defined on an IC die, then computational capacity increases, but the maximum number of transistors that can be defined on a semiconductor substrate is reached
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangements to three-dimensional vertical stacking of IC dies. By stacking multiple dies in the z-axis direction, the system achieves higher transistor density without increasing the footprint area, effectively adding a new dimension to the transistor arrangement space.
Solution Approach 2:
The patent implements nested structures where multiple IC dies are stacked within a compact three-dimensional package. Each die contains circuit blocks that are vertically aligned and interconnected, creating a nested arrangement where functional units are embedded within each other in the vertical dimension.
2Quantity of substance
If circuit blocks are placed close together to increase density, then transistor density improves, but wire length and power consumption increase
Solution Approach 1:
The patent uses vertical z-axis interconnects to connect circuit blocks across stacked dies. This vertical routing provides direct, short communication paths between vertically aligned circuit blocks, reducing the horizontal wire length that would be required in a planar arrangement and thereby reducing power consumption.
3Quantity of substance
If circuit blocks are placed close together to increase density, then transistor density improves, but I/O bottlenecks worsen
Solution Approach 1:
The patent introduces multiple I/O interfaces distributed across different dies in the vertical stack. This vertical distribution of I/O resources provides multiple parallel communication channels, eliminating the bottleneck that would occur with limited I/O interfaces in a planar arrangement.
Data Source
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AI summary
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.