3D Conductive Layers for Die Height Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor packaging solutions face challenges in thermal management due to die height differences, leading to increased thermal resistances and limited thermal design power capabilities, which are costly and inefficient.
Innovation Solution
The implementation of three-dimensional thermally conductive layers with varying thicknesses, using methods like cold spray or electroplating, directly on microelectronic devices to cover their entire footprint, thereby reducing hotspot formation and enhancing thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If recessed pedestals are implemented on stacked dies to address die height differences, then die height uniformity is improved, but thermal resistance increases and packaging cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar heat spreading to three-dimensional volumetric heat spreading by building up conductive material in vertical layers. Multiple conductive layers are stacked with varying thicknesses to fill the height differential between stacked dies and memory dies, creating a volumetric thermal management solution that maintains thermal contact across the entire die surface including edges.
Solution Approach 2:
The patent applies different thicknesses of conductive material to different regions of the stacked dies. The conductive layers are configured with varying thicknesses tailored to the specific height differences at different locations, ensuring optimal thermal contact and heat spreading throughout the package while addressing local height variations rather than applying a uniform solution.
2Shape
If thicker thermal interface material is used on stacked dies to address die height differences, then die height uniformity is improved, but thermal resistance increases
Solution Approach 1:
The patent changes the physical state and properties of the thermal interface material by replacing traditional TIM with highly conductive materials such as copper, silver, or diamond-like carbon. This parameter change in material conductivity allows for effective thermal management without requiring thick layers, thereby maintaining low thermal resistance while achieving height uniformity.
Solution Approach 2:
The patent employs composite thermal management structures combining multiple materials with different properties. The conductive layers may consist of copper, silver, or diamond-like carbon materials, potentially in combination with other substrates or interconnect structures, creating a composite system that optimizes both mechanical height compensation and thermal conductivity.
3Shape
If integrated heat spreader with recessed pedestals is implemented, then die height uniformity is improved, but packaging cost and complexity increase
Solution Approach 1:
The patent merges the functions of height compensation and thermal management into a single integrated structure. The conductive layers serve dual purposes: they fill the height differential between stacked dies and memory dies while simultaneously providing thermal conduction pathways. This consolidation eliminates the need for separate recessed pedestal structures, reducing packaging complexity and cost.
Solution Approach 2:
The conductive layers are designed to perform multiple functions simultaneously: mechanical height compensation, thermal conduction, and potentially electrical interconnection. This multi-functionality reduces the number of separate components needed in the packaging, thereby simplifying the overall package structure and reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces thermal resistances and increases thermal design power capabilities by ensuring uniform thermal conductivity across devices with different heights, improving overall package performance.
Implementation Method 1
three-dimensional buildup thermally conductive layers and methods of forming the same
Implementation Method 2
using methods like cold spray or electroplating
Implementation Method 3
using methods like cold spray or electroplating
Data Source
AI summary
Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.