3D Connectivity Die for Decoupled Compute and I/O Access
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Solution Overview
Problem
Planar programmable device architectures face challenges in incorporating additional services like hardened interconnects, which disrupt regular structures and complicate I/O bandwidth distribution, necessitating monolithic FPGA designs that require users to be aware of device architecture for optimal mapping.
Innovation Solution
A 3D stack of semiconductor dies with a connectivity die that includes configurable interconnects, allowing regular processing blocks to communicate with irregularly arranged I/O blocks without disrupting the fabric, enabling independent configuration and fair access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If monolithically compiled FPGA design is used to provide full I/O bandwidth to compute elements, then I/O bandwidth distribution is improved, but device architecture complexity increases and users must be aware of underlying device architecture
Solution Approach 1:
The device is segmented into multiple coarse-grained regions, each with its own local interconnect fabric. This segmentation allows independent configuration of each region without affecting others, reducing the complexity of monolithic compilation while maintaining full I/O bandwidth access through hierarchical interconnection.
Solution Approach 2:
Each coarse-grained region is equipped with local I/O blocks and local interconnect fabric, providing quality differentiation. This allows compute elements in each region to access local I/O resources directly, improving bandwidth distribution while reducing the complexity of global interconnect management.
2Device complexity
If coarse-grained regions with local I/O only are used, then device complexity is reduced, but communication between blocks is limited and users must map logic to specific regions
Solution Approach 1:
Multiple coarse-grained regions are merged through a hierarchical interconnect structure that combines local interconnect fabrics with global interconnect resources. This allows compute elements in different regions to communicate freely while maintaining the simplicity of local configuration within each region.
Solution Approach 2:
The interconnect fabric is designed to serve multiple functions: local communication within a region, global communication between regions, and I/O access. This universal interconnect structure enables versatile block communication without requiring users to map logic to specific regions, enhancing adaptability while keeping device complexity manageable.
3Productivity
If hardened interconnects are included in planar architectures, then I/O bandwidth is improved, but regular fabric structures are disrupted and timing characteristics worsen
Solution Approach 1:
The architecture transitions from planar to 3D stacking, allowing hardened interconnects and I/O blocks to be placed in separate vertical layers. This dimensional separation enables high-bandwidth I/O resources to coexist with regular fabric structures without disruption, maintaining timing characteristics while improving I/O bandwidth through three-dimensional integration.
Data Source
AI summary
Embodiments herein describe a 3D stack of dies (e.g., an active-on-active (AoA) stack) with a connectivity die that enables the decoupling of processing regions in coupled dies from each other and from the physical location of I/O blocks on an I/O die. For example, the first die may have a plurality of hardware processing blocks that are arranged in a regular manner (e.g., an array with rows and columns). The connectivity die can include interconnects that couple these hardware processing blocks to I/O blocks in a second die. These I/O blocks may be arranged in an irregular manner. The interconnects in the connectivity die can provide fair access so that processing blocks on a first side of the first die can access an I/O block on the opposite side of the second die without using resources for neighboring processing blocks.