3D Source-Drain Contacts for Strain-Tuned Stacked CMOS

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Solution Overview

Problem

Field-effect transistors (FETs), particularly in vertically stacked gate-all-around (GAA) transistor architectures, face challenges in inducing strain in nanoribbon channels, which affects the performance of PMOS and NMOS devices due to opposite strain requirements, leading to difficulties in achieving optimal mobility and performance.

Innovation Solution

The use of conductive materials like tungsten and cobalt for PMOS devices to induce compressive strain and molybdenum for NMOS devices to induce tensile strain, strategically positioned as 3D source and drain contacts, to improve hole and electron mobility respectively, within vertically stacked transistors in a CMOS architecture.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If vertically stacked GAA transistor architecture is used to increase device density, then device integration is improved, but inducing strain in nanoribbon channels becomes difficult

Engineering Contradiction:
Improvedevice integrationVSAvoidstrain induction
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies different conductive materials to source and drain contacts of PMOS and NMOS devices locally. PMOS contacts use tungsten for compressive strain while NMOS contacts use molybdenum for tensile strain, enabling localized strain optimization in vertically stacked GAA transistors without affecting other regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the material parameter (conductive material type) to control strain characteristics. By selecting materials with specific mechanical properties (tungsten for compression, molybdenum for tension), the patent optimizes carrier mobility in nanoribbon channels of vertically stacked devices.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If same conductive material is used for both PMOS and NMOS devices, then manufacturing is simplified, but optimal mobility for both device types cannot be achieved

Engineering Contradiction:
Improvematerial selectionVSAvoiddevice performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements local differentiation by using tungsten for PMOS source/drain contacts to induce compressive strain for improved hole mobility, while using molybdenum for NMOS source/drain contacts to induce tensile strain for improved electron mobility, thereby optimizing performance for each device type separately.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs different conductive materials (tungsten and molybdenum) for different device types within the same integrated structure. This composite approach allows simultaneous optimization of PMOS and NMOS devices with their respective strain requirements while maintaining a unified vertically stacked architecture.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the performance of PMOS and NMOS devices by optimizing strain within their channel regions, resulting in improved mobility and operational efficiency in integrated circuits.

Implementation Method 1

The first conductive material induces compressive strain on the channel region of the PMOS device

Methodology Applied
Scientific EffectCompressive strain: Compression

Implementation Method 2

The second conductive material induces tensile strain on the channel region of the NMOS device

Methodology Applied
Scientific EffectTensile strain: Tension

Data Source

PatentUS20230395718A13D source and drain contacts tuned for vertically stacked PMOS and nmos
Publication Date: 2023.12.07 INTEL CORP
  • US20230395718A1 patent drawing
  • US20230395718A1 patent drawing
  • US20230395718A1 patent drawing

AI summary

An integrated circuit structure includes a vertical stack including a first device, and a second device above the first device. The first device includes (i) a first source and first drain region, (ii) a first body laterally between the first source and drain regions, (iii) a first source contact including a first conductive material, and (iv) a first drain contact including the first conductive material. The second device includes (i) a second source and second drain region, (ii) a second body laterally between the second source and drain regions, (iii) a second source contact including a second conductive material, and (iv) a second drain contact including the second conductive material. In an example, the first and second conductive materials are compositionally different. In an example, the first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.