3D IC Face-to-Face Copper Bonding for Vertical Connectivity
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing and the limitations of Through-Silicon-Via (TSV) technology in achieving high vertical connectivity in 3D Integrated Circuits (ICs) pose challenges for reducing interconnect impact and enhancing performance and power efficiency in ICs.
Innovation Solution
The method involves face-to-face bonding of wafers with copper interconnecting layers and thinning the second crystalline substrate to less than 5 micrometers, along with forming vias with a radius of less than 1 micrometer, to improve vertical connectivity and reduce interconnect length in 3D ICs, potentially replacing TSVs with more efficient connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon-Via (TSV) technology is used to achieve vertical connectivity in 3D ICs, then interconnect functionality is provided, but the vertical connectivity density is limited and interconnect length is excessive
Solution Approach 1:
The patent transitions from conventional 2D planar interconnect architecture to a 3D stacked architecture where multiple semiconductor layers are vertically integrated. This dimensional change enables significantly higher vertical connectivity density by utilizing the third dimension (height) for interconnect routing, allowing numerous interconnect lines to pass through the vertical stack without occupying excessive lateral space.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor layers, each containing transistors and interconnect lines, are stacked and integrated within a single 3D IC package. Each layer is nested within the overall 3D structure, with through-layer vias penetrating through multiple nested layers to establish vertical electrical connections, thereby achieving high-density vertical interconnectivity.
2Ease of manufacture
If mask set cost is reduced for semiconductor manufacturing, then development cost decreases, but manufacturing precision and device quality may be compromised
Solution Approach 1:
The patent segments the semiconductor manufacturing process into multiple discrete layers that are fabricated separately and then stacked vertically. Each layer can be manufactured using standard, cost-effective mask sets without requiring expensive custom mask sets for the entire 3D structure. This segmentation allows each layer to be produced with adequate precision using conventional manufacturing techniques.
Solution Approach 2:
By moving to 3D stacking architecture, the patent reduces the lateral footprint requirements and allows standard mask sets to be used for each individual layer. The vertical integration approach enables manufacturing precision to be maintained through layer-by-layer fabrication rather than requiring complex single-layer masks for the entire device structure.
3Use of energy by moving object
If interconnect length is reduced in 3D ICs, then power consumption and signal delay decrease, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent utilizes vertical stacking to reduce interconnect length by routing signals through the thickness direction rather than across large lateral distances. Through-layer vias provide direct vertical pathways that significantly shorten the distance between functional blocks on different layers, thereby reducing power consumption and signal delay.
Solution Approach 2:
The patent segments the interconnect structure into horizontal interconnect lines on each layer and vertical through-layer vias connecting different layers. This segmented approach simplifies the manufacturing process by allowing standard planar fabrication techniques for horizontal lines and separate via formation processes for vertical connections, rather than requiring complex single-step patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides an order of magnitude improvement in vertical connectivity, reduces development costs, and enhances the yield and reliability of complex 3D ICs, addressing the limitations of current TSV technology and mask set costs.
Implementation Method 1
performing a face-to-face bonding of the second wafer on top of the first wafer, wherein the face-to-face bonding comprises copper to copper bonding
Implementation Method 2
thinning the second crystalline substrate to a thickness of less than 5 micrometers
Implementation Method 3
forming vias through the second crystalline substrate, wherein the vias have a radius of less than 1 micrometer
Data Source
AI summary
A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.