3D Interlocked Corrugated Capacitors for High-Density CMOS Decoupling
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Solution Overview
Problem
Conventional capacitor structures in integrated circuits require multiple patterning steps, leading to increased costs and insufficient capacitance per unit area, while also occupying valuable space, which hinders the scaling of semiconductor devices.
Innovation Solution
The implementation of 3D interlocked corrugated capacitor structures, which feature protrusions extending horizontally into the insulator material, allowing for simpler patterning and higher capacitance per unit area without occupying additional space, and can be integrated into advanced CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional capacitor structures are used, then fabrication process is well-established, but multiple patterning steps are required and capacitance per unit area is insufficient
Solution Approach 1:
The patent transitions from conventional planar capacitor structures to three-dimensional corrugated structures with vertical protrusions. This dimensional change allows capacitor electrodes to extend vertically into the insulator material, dramatically increasing the effective capacitance area per unit footprint while avoiding additional lateral patterning steps.
Solution Approach 2:
The patent employs corrugated surfaces with curved protrusions extending from the capacitor electrodes into the insulator material. These curved, three-dimensional surfaces provide increased surface area for capacitance formation compared to flat planes, enabling higher capacitance density without requiring more patterning steps.
2Manufacturing precision
If capacitor size is increased to provide sufficient capacitance, then capacitance per unit area improves, but valuable die space is occupied
Solution Approach 1:
By extending capacitor electrodes vertically into the insulator material through corrugated protrusions, the patent increases capacitance in the vertical dimension rather than expanding laterally. This allows sufficient capacitance to be achieved within a compact footprint, preserving valuable horizontal die space for other circuit elements.
Solution Approach 2:
The corrugated capacitor structures are nested within the existing BEOL layer architecture, with protrusions fitting into the insulator material volume. This nested three-dimensional configuration maximizes capacitance within the available vertical space between metal layers, avoiding occupation of additional horizontal die area.
3Ease of manufacture
If 3D interlocked corrugated capacitor structures are implemented, then capacitance per unit area increases and fabrication is simpler, but new fabrication techniques are required
Solution Approach 1:
The patent achieves high capacitance per unit area through vertical corrugated protrusions that extend into the insulator material. This three-dimensional configuration is formed using standard conformal deposition techniques applied to angled surfaces, leveraging existing fabrication capabilities to achieve enhanced capacitance without requiring fundamentally new manufacturing processes.
Solution Approach 2:
The patent forms the corrugated capacitor structures during the BEOL fabrication process before final interconnect formation. By pre-forming the three-dimensional capacitor structures with appropriate protrusions and insulation, the design cushions against future fabrication variability and ensures consistent capacitance values are achieved through standard subsequent processing steps.
Data Source
AI summary
Disclosed herein are IC devices with 3D interlocked corrugated capacitor structures. An example IC device includes a support structure (e.g., a substrate, a die, a wafer, or a chip), an insulator material over the support structure, and a first and a second corrugated capacitor structures extending into the insulator material, where a projection of at least one of the protrusions of the first corrugated capacitor structure onto a plane parallel to the support structure overlaps with a projection of at least one of the protrusions of the second corrugated capacitor structure onto the plane.