3D Cross-Coupled Gate Layout Without Dummy Transistors
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Solution Overview
Problem
Current 3D stacked semiconductor devices face challenges in achieving performance gains while maintaining a small chip size, as they often require dummy transistors in cross-coupled gate designs, which increase chip size and complexity.
Innovation Solution
A semiconductor device with a cross-coupled gate circuit design that eliminates the need for dummy transistors by strategically connecting gate lines between transistors in a 3D stacked structure, allowing for enhanced performance without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dummy transistors are used in cross-coupled gate design for 3D stacked devices, then the transistor integration density is improved, but the chip size increases
Solution Approach 1:
The patent applies 3D stacking to arrange transistor layers vertically across multiple levels, enabling cross-coupled gate connections between different stacked layers. This vertical dimensionality allows achieving higher integration density without proportionally increasing the horizontal chip footprint, as transistors are stacked in the Z-direction rather than spread out in the XY-plane.
Solution Approach 2:
The patent implements nested structures where gate lines are positioned within and between transistor layers in a hierarchical stacking arrangement. Multiple transistor layers are nested vertically, with gate lines interleaved between them, creating a compact nested configuration that maximizes transistor density within the available vertical space without requiring additional horizontal area.
2Reliability
If dummy transistors are added to cross-coupled gate layout, then the circuit functionality is ensured, but the manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for dummy transistors from the cross-coupled gate design by implementing direct gate line connections between stacked transistor layers. The gate lines are extended and interconnected through the stacked structure, providing the necessary cross-coupling functionality without requiring additional dummy transistor elements that would complicate the manufacturing process.
3Ease of manufacture
If traditional cross-coupled gate layout is used in 3D stacked devices, then the manufacturing process is simplified, but the performance gain is reduced
Solution Approach 1:
The patent transitions from traditional planar cross-coupled gate layouts to a 3D stacked configuration where gate lines connect transistors across multiple vertical layers. This dimensional change enables enhanced performance through improved gate control and tighter coupling between complementary transistors, while the manufacturing process remains relatively simplified by extending conventional fabrication techniques into the vertical dimension.
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.