3D Cross FET Power Routing With Backside TSV Connections
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Solution Overview
Problem
Modern semiconductor chip design faces challenges such as voltage droop, capacitive coupling, electro migration, and increased semiconductor fabrication complexity due to issues like leakage currents and power signal routing across multiple metal layers, which delay design completion and affect time to market.
Innovation Solution
The implementation of Cross Field Effect Transistors (FETs) with a backside power metal rail and micro through silicon via (TSV) to connect n-type and p-type devices across frontside and backside metal layers, reducing on-die area and semiconductor fabrication complexity, while improving wafer yield and reducing voltage droop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power signals are routed across multiple metal layers, then power distribution is achieved, but the distance between contacts increases and floorplan area expands
Solution Approach 1:
The patent utilizes the third dimension by routing power signals through vertical through-silicon vias (TSVs) that penetrate the substrate, transitioning from planar 2D routing to 3D vertical routing. This allows power connections to be made directly beneath active devices rather than traversing multiple horizontal metal layers, significantly reducing the lateral distance and floorplan area required for power distribution.
Solution Approach 2:
The patent inverts the conventional power routing approach by bringing power contacts from the backside of the substrate rather than from the frontside. This inversion allows power signals to be delivered directly to the root of the interconnect tree at the device location, eliminating the need for long lateral traverses across the die and reducing floorplan constraints.
2Ease of manufacture
If conventional transistors are used, then manufacturing is simpler, but voltage droop and leakage currents increase
Solution Approach 1:
The patent employs cross-field effect transistors (CFETs) that utilize vertical electric field modulation to control current flow, fundamentally changing the transistor operation parameter from lateral field effect to vertical field effect. This parameter change enables superior control over leakage currents and voltage droop while maintaining compatibility with existing semiconductor manufacturing processes through vertical device stacking.
Solution Approach 2:
The patent implements a composite transistor structure combining n-type and p-type semiconductor materials in a vertical stacked configuration, where each material layer serves a specific function. This composite structure enables independent optimization of electron and hole transport properties, achieving reduced voltage droop and leakage while maintaining manufacturing feasibility through established CMOS fabrication techniques.
3Reliability
If design constraints are applied to reduce voltage droop, then power delivery improves, but design time and time to market increase
Solution Approach 1:
The patent incorporates backside power contacts and vertical interconnect structures during the initial substrate fabrication stage, performing power distribution infrastructure setup before device placement and interconnect routing. This preliminary action eliminates the need for subsequent iterative design adjustments to address voltage droop, significantly reducing design time while ensuring optimal power delivery from the outset.
Data Source
AI summary
An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit uses Cross field effect transistors (FETs) with a first device, such as n-type device, having a first channel oriented in a first direction and connected to a ground reference voltage level provided by a backside metal layer. The Cross FETs also use a second device, such as the p-type device, having a second channel oriented in a second direction orthogonal to the first direction and connected to a power supply reference voltage level provided by a frontside metal layer. A micro through silicon via (TSV) traverses the silicon substrate layer in order to be placed between the backside metal layer and the source region of an n-type device. The power connections reduce on-die area, reduces semiconductor fabrication complexity, which improves wafer yield, and reduces voltage droop, which increases performance.