3D Cross-Point Memory for Granular Bit Access
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Solution Overview
Problem
Conventional memory devices can only address fixed-size multiple-bit data structures, limiting flexibility and efficiency in data access, especially in matrix operations where granular data manipulation is desired.
Innovation Solution
A compute device with a three-dimensional cross-point architecture that allows individual addressability of bits, enabling the media access circuitry to read and write data of arbitrary sizes by mapping logical rows and columns to physical tiles, eliminating the need for intermediary transpose operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional memory devices address fixed-size multiple-bit data structures, then device complexity is reduced and ease of operation is improved, but adaptability and productivity are limited
Solution Approach 1:
The memory device is segmented into multiple banks, with each bank containing multiple arrays of memory cells. This hierarchical segmentation allows the system to address individual bits through specific bank-array-cell combinations, enabling granular data access while maintaining organized structure. The segmentation principle resolves the contradiction by providing bit-level accessibility without requiring a completely complex addressing scheme.
Solution Approach 2:
The patent introduces a new dimension of addressability by organizing memory cells in three-dimensional space with multiple banks and arrays within each bank. This multi-dimensional organization allows individual bits to be addressed through combinations of bank selects, array selects, and cell addresses, effectively adding spatial dimensions to the addressing scheme and enabling flexible data access patterns.
2Productivity
If conventional memory devices use fixed-size data structures, then device complexity is reduced, but productivity and efficiency in matrix operations deteriorate
Solution Approach 1:
The memory architecture is divided into multiple banks and arrays, allowing matrix operations to be performed on segmented data. Each bank can handle specific portions of matrix data, enabling parallel processing of matrix elements. This segmentation enables efficient matrix multiplication and other linear algebra operations by allowing simultaneous access to multiple data elements.
Solution Approach 2:
The memory device is designed with universal functionality to support both traditional fixed-size data structure operations and granular bit-level operations. The same bank-array-cell structure can accommodate various data access patterns including row-major and column-major ordering, making the memory system versatile for different computational workloads including matrix operations, vector operations, and scalar operations.
3Adaptability or versatility
If conventional memory devices address fixed-size data structures, then ease of operation is improved, but adaptability for granular data manipulation deteriorates
Solution Approach 1:
The hierarchical bank-array-cell structure provides natural segmentation that facilitates granular data manipulation. Each level of segmentation (bank, array, cell) can be independently selected and controlled, allowing precise access to individual bits while maintaining a systematic approach to data manipulation. This segmented structure makes granular operations more manageable despite the increased adaptability requirements.
Solution Approach 2:
The patent introduces intermediary control mechanisms including bank select signals, array select signals, and decode logic that mediate between the control unit and individual memory cells. These intermediaries simplify the operation of granular data manipulation by providing structured interfaces and automated addressing, reducing the complexity burden on the user while enabling precise bit-level access.
4Loss of time
If conventional memory devices use fixed-size data structures, then device complexity is reduced, but loss of time in data access increases
Solution Approach 1:
The segmented bank-array-cell structure enables parallel data access by allowing multiple banks to be accessed simultaneously. This segmentation allows the memory system to service multiple memory requests in parallel, reducing the overall time required for data access operations. The hierarchical structure facilitates time-efficient access patterns for both sequential and random data retrieval.
Solution Approach 2:
The memory architecture supports continuous data access operations by maintaining ready states across multiple banks and arrays. The design enables pipelined operations where while one bank is being accessed, other banks can be prepared or already servicing requests. This continuity of useful action reduces idle time and improves overall data access throughput despite the complex multi-bank structure.
Data Source
AI summary
Technologies for addressing individual bits in memory include a device having a memory that includes partitions that each have tiles, in which each tile stores an individual bit. The device also includes circuitry to receive a request to access (e.g., read or write) a sequence of bits in a partition. The request specifies a logical row or column address. A corresponding tile is determined from the logical row or column address and for each bit in the sequence. The corresponding tile is accessed to read or write the bit therein.