3D Cross-Point Memory Lithography Reduction via Selective Etching
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Solution Overview
Problem
The high cost and time-consuming nature of lithographic patterning steps in semiconductor manufacturing for constructing 3D cross-point memory arrays, particularly for fine geometries, necessitates an alternative method for forming these arrays without the need for patterning at each layer.
Innovation Solution
The method involves depositing a patterned hard mask with first trenches etched through multiple layers, followed by orthogonal second trenches, and selective undercut etching to remove layers except the orthogonal metal layers, resulting in a 3D cross-point array with memory material only at intersections, thereby eliminating the need for lithographic patterning at each layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithographic patterning is used at each layer to construct 3D cross-point memory arrays, then manufacturing precision is improved, but manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent segments the manufacturing process into distinct phases: first forming all metal layers without patterning, then performing a single lithography step to create hard masks, followed by etching operations that selectively remove materials. This segmentation allows multiple layers to be processed simultaneously rather than sequentially, improving productivity while maintaining precision through the hard mask definition.
Solution Approach 2:
The patent performs preliminary deposition of all metal layers (first metal layers and second metal layers) and insulation layers before any lithographic patterning. This preliminary action establishes the complete 3D structure, and subsequent etching operations simply remove unwanted portions, eliminating the need for repeated lithography steps at each layer and significantly reducing production time.
2Manufacturing precision
If lithographic patterning is used at each layer to construct 3D cross-point memory arrays, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple lithography operations into a single lithographic patterning step by performing all metal layer depositions and insulation layer formations before patterning. The hard mask is formed once and used to define patterns for multiple layers simultaneously through selective etching, reducing the number of expensive lithography steps while maintaining fine geometry precision.
Solution Approach 2:
All material depositions are performed preliminarily before any lithographic patterning, establishing the complete layered structure. This preliminary action eliminates the need for repeated lithography steps at each layer, significantly reducing manufacturing cost while maintaining precision through the single hard mask definition step.
3Manufacturing precision
If lithographic patterning is performed at each layer, then layer-specific patterns are achieved, but the number of processing steps increases
Solution Approach 1:
The patent segments the process into material deposition phase (no patterning) and pattern definition phase (single lithography step followed by selective etching). This segmentation allows all layers to be formed uniformly first, then patterns are defined once and selectively applied to different layers through etching, reducing the total number of processing steps while achieving layer-specific patterns.
Solution Approach 2:
All material depositions are performed preliminarily before any lithographic patterning, establishing the complete layered structure. This preliminary action eliminates the need for repeated lithography steps at each layer, significantly reducing the number of processing steps while maintaining layer-specific pattern definition through selective etching operations.
Data Source
AI summary
The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.