3D Crosspoint Memory Multi-Level Programming Readout
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Solution Overview
Problem
The production of viable multi-level cell 3D crosspoint memory arrays is hindered by limited read window budget, unsatisfactory program state retention, and read and write disturb issues, requiring demanding refresh approaches that affect overall performance.
Innovation Solution
The implementation of 3D crosspoint memory arrays with multi-level cells that utilize tunable program windows through varying write current and pulse-width, along with a read algorithm featuring controllable current and polarity for disturb-immune, refresh-embedded readout, enabling adequate program windows and algorithmic simplicity for analog tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell 3D crosspoint memory arrays are implemented, then storage density is improved, but read window budget becomes limited and program state retention becomes unsatisfactory
Solution Approach 1:
The patent implements dynamic read algorithms that adjust read voltage levels and pulse widths based on the programmed state of memory cells. The read operation uses multiple voltage levels (Vread1, Vread2, Vread3) that are dynamically selected based on the expected program state, allowing the system to adapt to different retention conditions and maintain reliability across varying storage density configurations.
Solution Approach 2:
The patent changes multiple parameters including read voltage levels, pulse widths, and current magnitudes to optimize both storage density and program state retention. By varying these parameters dynamically during read operations, the system can maintain adequate retention characteristics while achieving high storage density through multi-level cell configurations.
2Quantity of substance
If multi-level cell programming is implemented, then storage capacity is improved, but read and write disturb issues increase
Solution Approach 1:
The patent segments the read operation into multiple distinct voltage levels and stages (first read voltage, second read voltage, third read voltage) with different magnitudes. This segmentation allows the system to perform sequential reads at increasing voltage levels, minimizing disturb effects during each individual read operation while still enabling complete state detection for high storage capacity.
Solution Approach 2:
The patent applies partial read actions by using multiple read voltage levels where not all voltage levels are applied to all cells simultaneously. Instead, different voltage levels are applied selectively based on the expected program state, reducing the excessive action that would cause read disturb while maintaining the ability to detect all storage states.
3Reliability
If demanding refresh approaches are used to maintain program state retention, then reliability is improved, but overall performance deteriorates
Solution Approach 1:
The patent performs preliminary actions by applying multiple read voltages in a predetermined sequence during the read operation itself. This preliminary multi-voltage read approach ensures that program state retention is verified and maintained as part of the normal read operation, eliminating the need for separate refresh operations and thus maintaining both reliability and performance.
Solution Approach 2:
The read operation itself provides the refresh function by using multiple voltage levels that reinforce the programmed state during reading. The memory cells serve their own refresh needs through the multi-level read algorithm, eliminating the need for dedicated refresh operations and thereby maintaining high overall performance while ensuring program state retention.
4Measurement precision
If multiple read voltages are applied to determine program state, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where the result of each read voltage application influences the selection of subsequent read voltages. The read algorithm uses feedback from current measurements at each voltage level to determine whether to proceed to the next voltage level or conclude the read operation, achieving high measurement precision through a structured feedback-based approach that manages device complexity.
Data Source
AI summary
A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.