3D Dataflow Architecture With RAPCs for Programmable Routing
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Solution Overview
Problem
Existing multiprocessor architectures face challenges in achieving fast computing with flexibility, minimizing unintended interactions, and optimizing data flow routing while handling complex algorithms efficiently.
Innovation Solution
A 3D dataflow architecture using Reconfigurable Algorithmic Pipeline Cores (RAPCs) with a pipelined pseudo 3D dataflow routing structure, allowing simultaneous data processing and reducing bottlenecks through a simplified hardware design that eliminates unnecessary CPU components and enables flexible algorithm execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multiprocessor architectures are used, then computing speed can be achieved, but flexibility and unintended interactions between program elements increase
Solution Approach 1:
The system segments the multiprocessor architecture into distinct computational elements (CEs) organized in a grid, where each CE is independent and can be individually configured. This segmentation allows parallel processing for speed while maintaining clear boundaries that reduce unintended interactions, and the modular nature enables flexible reconfiguration for different algorithms.
Solution Approach 2:
The architecture implements dynamic reconfigurability where computational elements and their interconnections can be programmatically adjusted during operation. This allows the system to adapt to different computational tasks and algorithms, providing flexibility while maintaining optimized performance paths for each specific computation.
2Adaptability or versatility
If complex routing structures are used to handle data flow, then algorithm flexibility increases, but data flow bottlenecks and latency increase
Solution Approach 1:
Each computational element in the grid has standardized local interfaces and data flow paths, creating uniform local quality throughout the architecture. This standardization enables predictable data flow timing while the overall grid structure provides flexibility for different algorithms by combining these uniform local units in various configurations.
3Adaptability or versatility
If more CPU components are added to handle complex algorithms, then algorithm capability increases, but hardware size and complexity increase
Solution Approach 1:
The computational elements are designed as universal units that can perform multiple computational functions through reconfiguration. Each CE can be programmed to execute different operations, eliminating the need for specialized hardware for each algorithm type. This multi-functionality provides algorithm capability while maintaining relatively simple, standardized hardware components.
Data Source
AI summary
A plurality of simplified CPUs (RAPCs) are provided with data from an input or from memory. The first RAPC completes its simplified task, then turns and hands the data downstream to the next RAPC. Data is routed in a programmable, 3D routing scheme through the array, allowing many simultaneous operations to complete an algorithm as in an assembly line. Completed results go downstream for use as needed.