3D Decoupling Integration Within Hole in Motherboard
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Solution Overview
Problem
Conventional packaging solutions for small form factor electronic devices face challenges with high-frequency noise propagation, leading to electromagnetic interference (EMI) and radio frequency interference (RFI), which results in inefficient PCB area utilization and ineffective capacitor placement due to the z-height limitations of decoupling land side capacitors (LSCs).
Innovation Solution
The implementation of three-dimensional (3D) decoupling integration within a hole in the motherboard (HiMB) by embedding 3D capacitors vertically between the EMI shield and the HiMB sidewalls, reducing the need for edge capacitors and minimizing the z-height of LSCs, thereby optimizing PCB area utilization and improving miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If decoupling land side capacitors (LSCs) are used to suppress high-frequency noise, then EMI and RFI are reduced, but the z-height of LSCs exceeds the z-height of solder balls requiring a HiMB to be formed
Solution Approach 1:
The patent transitions from conventional planar capacitor placement to three-dimensional vertical integration by forming vias through the substrate and placing capacitors in the vertical dimension, allowing capacitors to be positioned below the substrate level without increasing z-height
Solution Approach 2:
The patent embeds capacitors within the substrate structure by forming vias and placing capacitors in the vertical space below the substrate, effectively nesting the capacitor structure within the existing package footprint without requiring additional external space
2Length of stationary object
If a HiMB is formed to accommodate LSCs, then the z-height profile is satisfied, but PCB area utilization decreases due to unutilized PCB area
Solution Approach 1:
The patent moves capacitor placement from the horizontal PCB plane to the vertical dimension by forming vias through the substrate and placing capacitors below the substrate level, thereby utilizing the vertical space that would otherwise be wasted and improving PCB area utilization
Solution Approach 2:
The patent extracts the capacitor placement function from the traditional PCB surface and relocates it to the vertical space below the substrate through via formation, separating the capacitor placement requirement from the PCB area constraint
3Length of stationary object
If edge capacitors are placed on the edges of the motherboard, then the HiMB and EMI shield requirements are met, but the capacitor placement becomes ineffective
Solution Approach 1:
The patent places capacitors in specific localized regions directly beneath the substrate where they are most effective for noise suppression, rather than distributing them along the edges, ensuring optimal local decoupling performance where it is most needed
Data Source
AI summary
Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).