3D True Time Delay Layout for High-Q Compact RF Delay Paths
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Solution Overview
Problem
Existing three-dimensional true time delay systems face challenges in maintaining a high quality factor while minimizing the area required, especially when the number of phase array antennas increases.
Innovation Solution
A three-dimensional true time delay system is developed by three-dimensionally forming passive elements on a glass substrate, including a true time delay package with a capacitor and inductor, and a delay element unit manufactured by forming solenoid-shaped via holes in the glass substrate and filling them with a conductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of phase array antennas is increased, then the beam steering capability is improved, but the area of the true time delay device increases and the quality factor decreases
Solution Approach 1:
The patent transitions from planar two-dimensional layout to three-dimensional vertical stacking of passive elements (inductors, capacitors, resistors) on glass substrates. This dimensional change allows multiple delay channels to be stacked vertically, significantly reducing the horizontal area occupied by the true time delay device while accommodating an increased number of phase array antennas.
Solution Approach 2:
The patent implements a multi-layer stacked architecture where passive elements are nested vertically across multiple glass substrates. Each layer contains complete RLC circuits, and layers are stacked to form compact three-dimensional delay channels. This nesting approach allows the system to scale the number of antennas by adding vertical layers rather than expanding horizontally.
2Adaptability or versatility
If the number of phase array antennas is increased, then the beam steering capability is improved, but the quality factor of the true time delay device decreases
Solution Approach 1:
By moving to three-dimensional vertical stacking, the patent reduces the horizontal trace length of RF signals and minimizes parasitic inductance and capacitance associated with long planar connections. The vertical interconnections through via holes provide shorter, more direct signal paths, reducing energy loss and maintaining higher quality factors even as the number of antenna channels increases.
Solution Approach 2:
The patent uses glass substrates with specific dielectric properties combined with metal conductors and via hole structures to create composite three-dimensional RLC circuits. The glass material provides stable dielectric characteristics with low loss, while the metallic via holes and trace patterns provide controlled inductance and resistance, collectively maintaining high quality factor across multiple stacked layers.
3Area of stationary object
If passive elements are formed in three-dimensions on a glass substrate, then the area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the true time delay device into multiple discrete glass substrate layers, each containing specific passive elements (inductors, capacitors, resistors). Each layer can be manufactured and characterized independently, then stacked and interconnected through via holes. This segmentation reduces the complexity of manufacturing the entire three-dimensional structure in one process and allows for modular assembly and testing.
Solution Approach 2:
The patent uses glass substrates as intermediary carriers that provide mechanical support, electrical insulation, and precise positioning for the passive elements. The glass layers act as mediators between the metallic conductive patterns and via holes, enabling three-dimensional integration while maintaining manufacturing feasibility through standard glass processing techniques and controlled via hole formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for an increased quality factor while reducing the area required, effectively addressing the limitations of existing systems by enhancing the delay performance in a compact form.
Implementation Method 1
a delay element unit three-dimensionally manufactured on a glass substrate to additionally delay the RF signals transferred from the true time delay package, wherein the delay element unit may be manufactured by forming solenoid-shaped via holes in the glass substrate and filling the solenoid-shaped via hole with a conductor
Implementation Method 2
a true time delay package that includes a capacitor and an inductor to delay applied RF signals as much as a predetermined delay time
Implementation Method 3
a true time delay package that includes a capacitor and an inductor to delay applied RF signals as much as a predetermined delay time
Data Source
AI summary
A three-dimensional true time delay system includes: a true time delay package that includes a capacitor and an inductor to delay applied RF signals as much as a predetermined delay time; and a delay element unit three-dimensionally manufactured on a glass substrate to additionally delay the RF signals transferred from the true time delay package, wherein the delay element unit is manufactured by forming solenoid-shaped via holes in the glass substrate and filling the solenoid-shaped via hole with a conductor.