3D Die Backside Power Wiring for Shorter TSV Power Paths
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Solution Overview
Problem
Existing semiconductor devices with backside power delivery suffer from undesirable voltage loss due to lengthy power delivery pathways, particularly in three-dimensional dies, which affect energy efficiency.
Innovation Solution
The semiconductor device incorporates a shortened power delivery pathway by arranging backside BEOL wiring such that through-silicon vias (TSVs) contact the backside wiring more deeply within the die, eliminating the need for power to travel to the uppermost surface and back, and includes a combination of non-shortened and shortened TSVs to maintain efficient power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is delivered through the uppermost surface and back down to FEOL devices, then power can be supplied to front end of line devices, but the power delivery pathway becomes lengthy causing voltage loss
Solution Approach 1:
The patent inverts the conventional power delivery approach by delivering power from the backside of the wafer directly to the FEOL devices through through-wafer vias, rather than delivering power from the frontside through the uppermost surface and back down. This inversion shortens the power delivery pathway and reduces voltage loss while maintaining effective power supply to the devices.
2Loss of energy
If through-wafer vias are used to deliver power from backside, then power delivery pathway is shortened, but manufacturing complexity increases
Solution Approach 1:
The patent segments the via structure into two distinct types: through-wafer vias for power delivery that extend completely through the wafer thickness, and partial vias that extend only partially through the wafer. This segmentation allows optimization of power delivery pathways while managing manufacturing complexity by using different via configurations for different functional requirements.
Solution Approach 2:
The patent applies local quality by using through-wafer vias specifically in regions where short power delivery pathways are critical (near the backside contact), while using partial vias in other regions. This localized approach optimizes power delivery efficiency where needed while reducing overall manufacturing complexity by not requiring all vias to be through-wafer structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces voltage loss and improves energy efficiency by shortening the power delivery pathway, enhancing the performance of three-dimensional dies.
Implementation Method 1
a first via extending through the first dielectric material and electrically connected with the backside wiring such that a first power delivery pathway delivers power to a first front end of line device through the first via and the backside wiring
Data Source
AI summary
A semiconductor device includes a wafer having a frontside, a backside, and front end of line (FEOL) devices arranged on the frontside. The semiconductor device includes a first dielectric material coupled to the frontside and including frontside wiring electrically connected to the FEOL devices. The semiconductor device includes a second dielectric material coupled to the backside and including backside wiring electrically connected to the FEOL devices. The semiconductor device includes a first and second vias extending through the first dielectric material and electrically connected with the backside wiring such that a first power delivery pathway delivers power to a first FEOL device through the first via and the backside wiring and a second power delivery pathway delivers power to a second FEOL device through the second via and the backside wiring. The first power delivery pathway is shorter than the second power delivery pathway.