3D Semiconductor Die Layout for Integrated Compute and Memory Retention
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Solution Overview
Problem
Current semiconductor die manufacturing processes separate high-speed computing and long-term storage devices, leading to propagation delays and increased processing time due to data transfer between computing and storage memory devices.
Innovation Solution
A 3D semiconductor die is formed with a first set of semiconductor devices having a low workfunction for high-speed computing and a second set with a high workfunction for long-term storage, integrated monolithically to reduce propagation losses and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-speed computing devices and long-term storage devices are manufactured on separate dies, then each device can be optimized for its specific function, but propagation delays and processing time increase due to data transfer between separate memory devices
Solution Approach 1:
The patent combines high-speed computing devices and long-term storage devices into a single monolithic semiconductor die, eliminating the need for data transfer between separate dies. This integration directly reduces propagation delay and improves data fidelity by keeping computing and storage functions co-located on the same substrate.
Solution Approach 2:
The patent transitions from a 2D planar integration to 3D vertical stacking architecture, where computing devices and storage devices are stacked in different layers within the same die. This dimensional change allows both device types to coexist in close proximity without interfering with each other's electrical connections, reducing propagation delay while maintaining functional optimization.
2Ease of manufacture
If separate dies are used for computing and storage devices, then manufacturing processes can be optimized for each device type, but manufacturing complexity and costs increase due to interposer-based chip integration
Solution Approach 1:
The patent merges computing and storage device fabrication into a single monolithic manufacturing process, eliminating the need for separate dies and interposer-based integration. This reduces manufacturing complexity and costs while still allowing each device type to be optimized through selective material and structure design within the same die.
Solution Approach 2:
The patent applies local quality by using different materials, doping concentrations, and structural configurations in different regions of the monolithic die. Computing devices use materials and structures optimized for high-speed operation, while storage devices use materials and structures optimized for data retention, all within the same manufactured die.
3Adaptability or versatility
If data is transferred between computing and storage memory devices on separate dies, then functional separation is maintained, but processing time increases
Solution Approach 1:
The patent merges computing and storage functions into a single die to eliminate data transfer delays, while maintaining functional separation through 3D vertical stacking and distinct device regions. This allows both functions to operate simultaneously with direct interconnects, improving processing speed without sacrificing functional versatility.
Solution Approach 2:
By stacking computing and storage devices in different vertical layers, the patent maintains functional separation while enabling direct, short-distance electrical connections between layers. This 3D architecture eliminates the need for long-distance data transfer across separate dies, significantly improving processing speed while preserving the adaptability of having distinct computing and storage functions.
Data Source
AI summary
A semiconductor die comprises a first set of semiconductor devices disposed at a first location of the semiconductor die and a second set of semiconductor devices disposed at a second location of the semiconductor die different from the first location. Each of the first set of semiconductor devices have a first workfunction to cause each of the first set of semiconductor devices to store memory for a first time period. Moreover, each of the second set of semiconductor devices have a second workfunction that is higher greater than the first workfunction to cause each of the second set of semiconductor devices to store memory for a second time period greater than the first time period.