3D Die Stack Direct Bonding Without TSVs or Micro-Bumps
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Solution Overview
Problem
Current 3D die stacking technologies using micro-bumps and through-silicon vias (TSVs) increase manufacturing complexity and cost, and affect device performance, necessitating additional keep out zones.
Innovation Solution
A semiconductor package with direct bonding between interconnect structures using anisotropic conductive structures, such as anisotropic conductive film or paste, and thermal-compression bonding technology, eliminating the need for metal bumps and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If micro-bumps and TSVs are used for 3D die stacking, then chip connection and signal transmission are achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the TSV structure from the conventional 3D stacking process. By using direct bonding between semiconductor wafers without forming TSVs, the manufacturing process is simplified while maintaining electrical connection functionality through alternative interconnect structures on the wafer surfaces.
Solution Approach 2:
The patent merges the bonding process with the interconnect formation by directly bonding wafers with exposed interconnect structures. This eliminates the need for separate TSV formation and filling steps, combining multiple functions into a more integrated process flow.
2Reliability
If micro-bumps and TSVs are used for 3D die stacking, then chip connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive TSV formation process from the manufacturing flow. By using direct wafer bonding with surface interconnects, materials and process steps associated with TSV drilling, lining, and filling are eliminated, reducing overall manufacturing cost.
Solution Approach 2:
The patent employs simpler, more cost-effective interconnect structures that can be formed using standard semiconductor fabrication processes rather than requiring complex TSV and micro-bump technologies, thereby reducing material and processing costs.
3Reliability
If TSVs are used for signal transmission, then 3D stacking is enabled, but device performance is affected requiring additional keep out zone
Solution Approach 1:
The patent transitions from vertical TSV signal transmission to lateral surface interconnect transmission. By forming interconnect structures on the wafer surface that extend beyond the active die area, signals can be transmitted without requiring deep vertical vias, thereby reducing the keep-out zone requirement.
Solution Approach 2:
The patent segments the interconnect function from the vertical stacking structure by using surface-mounted interconnect elements. This allows signal transmission paths to be separated from the TSV alignment requirements, reducing the restrictive keep-out zones needed for TSV-based signaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces manufacturing complexity and cost while maintaining device performance, making it suitable for low pin count applications like Display Driver Integrated Circuits (DDICs).
Implementation Method 1
The plurality of first connecting elements are electrically connected to the plurality of second connecting elements through an anisotropic conductive structure
Implementation Method 2
a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die
Data Source
AI summary
A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.